INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4520B
MSI
Dual binary counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Dual binary counter
DESCRIPTION
The HEF4520B is a dual 4-bit internally synchronous
binary counter. The counter has an active HIGH clock
input (CP
0
) and an active LOW clock input (CP
1
), buffered
outputs from all four bit positions (O
0
to O
3
) and an active
HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH
transition of the CP
0
input if CP
1
is HIGH or the HIGH to
HEF4520B
MSI
LOW transition of the CP
1
input if CP
0
is low. Either CP
0
or
CP
1
may be used as the clock input to the counter and the
other clock input may be used as a clock enable input. A
HIGH on MR resets the counter (O
0
to O
3
= LOW)
independent of CP
0
, CP
1
.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.2 Pinning diagram.
HEF4520BP(N):
HEF4520BD(F):
HEF4520BT(D):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic (SOT109-1)
(SOT109-1)
Fig.1 Functional diagram.
( ): Package Designator North America
PINNING
CP
0A
, CP
0B
CP
1A
, CP
1B
MR
A
, MR
B
O
0A
to O
3A
O
0B
to O
3B
clock inputs (L to H triggered)
clock inputs (H to L triggered)
master reset inputs
outputs
outputs
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
2
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Philips Semiconductors
January 1995
Dual binary counter
Fig.3 Logic diagram (one counter).
FUNCTION TABLE
3
Product specification
CP
0
CP
1
MR
MODE
H
L
counter advances
L
L
counter advances
X
L
no change
X
L
no change
L
L
no change
H
L
no change
X
X
H
O
0
to O
3
= LOW
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
HEF4520B
MSI
Philips Semiconductors
Product specification
Dual binary counter
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
CP
0
, CP
1
→
O
n
HIGH to LOW
5
10
15
5
LOW to HIGH
MR
→
O
n
HIGH to LOW
Output transition
times
HIGH to LOW
5
10
15
5
LOW to HIGH
Minimum CP
0
pulse width; LOW
Minimum CP
1
pulse width; HIGH
Minimum MR
pulse width; HIGH
Recovery time
for MR
Set-up times
CP
0
→
CP
1
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
CP
1
→
CP
0
Maximum clock
pulse frequency
10
15
5
10
15
January 1995
f
max
t
su
t
su
t
RMR
t
WMRH
t
WCPH
t
WCPL
60
30
20
60
30
20
30
20
16
50
30
20
50
30
20
50
30
20
8
15
20
4
t
TLH
t
THL
60
30
20
60
30
20
30
15
10
30
15
10
15
10
8
25
15
10
25
15
10
25
15
10
16
30
40
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
10
15
5
10
15
t
PHL
t
PLH
t
PHL
110
50
40
110
50
40
75
35
25
220
100
80
220
100
80
150
70
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL MIN.
TYP. MAX.
HEF4520B
MSI
TYPICAL EXTRAPOLATION
FORMULA
83 ns
+
(0,55 ns/pF) C
L
39 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
83 ns
+
(0,55 ns/pF) C
L
39 ns
+
(0,23 ns/pF) C
L
32 ns
+
(0,16 ns/pF) C
L
48 ns
+
(0,55 ns/pF) C
L
24 ns
+
(0,23 ns/pF) C
L
17 ns
+
(0,16 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
10 ns
+
(1,0 ns/pF) C
L
9 ns
+
(0,42 ns/pF) C
L
6 ns
+
(0,28 ns/pF) C
L
see also waveforms
Figs 4 and 5
Philips Semiconductors
Product specification
Dual binary counter
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
input transition times
≤
20 ns
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
850 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
3 800 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
10 200 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
HEF4520B
MSI
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
Fig.4 Waveforms showing recovery time for MR; minimum CP
0
, CP
1
and MR pulse widths.
January 1995
5
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