INTEGRATED CIRCUITS
DATA SHEET
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•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4731B; HEF4731V
LSI
Quadruple 64-bit static shift register
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Quadruple 64-bit static shift register
DESCRIPTION
The HEF4731B and HEF4731V are quadruple 64-bit static
shift registers each with separate serial data inputs (D
A
to
D
D
), clock inputs (CP
A
to CP
D
) and data outputs (O
63A
to
O
63D
) from the 64th register position.
HEF4731B; HEF4731V
LSI
Recommended supply voltage range for HEF4731B is 3 to
15 V and for HEF4731V is 4,5 to 12,5 V.
Data are shifted to the next stage on the negative-going
transitions of the clock. Low impedance outputs are
provided for direct interface to TTL.
Fig.2 Pinning diagram.
HEF4731BP;
HEF4731VP(N):
HEF4731BD;
HEF4731VD(F):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
( ): Package Designator North America
FAMILY DATA, I
DD
LIMITS category LSI
Fig.1 Functional diagram.
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Quadruple 64-bit static shift register
HEF4731B; HEF4731V
LSI
Fig.3 Logic diagram (one of 64-bits shift register).
The values given at V
DD
= 15 V in the following DC
and AC characteristics, are not applicable to the HEF4731V,
because of its reduced supply voltage range.
DC CHARACTERISTICS
V
SS
= 0 V; V
I
= V
SS
or V
DD
T
amb
(°C)
V
DD
V
Output (source)
current
HIGH
Output (sink)
current
LOW
5
5
10
15
4,75
10
15
0,4
0,5
1,5
I
OL
V
OL
V
V
OH
V
2,5
4,6
9,5
13,5
−I
OH
SYMBOL
−40
MIN.
3
1
3
10
2,3
6,0
20,0
MAX.
+
25
MIN.
2,5
0,85
2,5
8,5
2,0
5,0
18,0
MAX.
+
85
MIN.
2,0
0,65
2,0
6,5
1,6
4,0
14,0
MAX.
mA
mA
mA
mA
mA
mA
mA
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
input transition times
≤
20 ns
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
13 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
55 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
140 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load capacitance (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
3
Philips Semiconductors
Product specification
Quadruple 64-bit static shift register
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
CP
→
O
63
HIGH to LOW
5
10
15
5
LOW to HIGH
Transition times O
63
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
Minimum clock
pulse width; HIGH
Set-up time
D
→
CP
Hold time
D
→
CP
Maximum clock
pulse frequency
10
15
5
10
15
5
10
15
5
10
15
5
10
15
f
max
t
hold
t
su
t
WCPH
200
75
50
25
15
15
50
30
20
2.25
6
9
t
TLH
t
THL
t
PLH
t
PHL
115
55
40
130
65
45
30
12
10
40
20
15
80
30
20
−5
−5
−5
20
10
5
6
16
25
230 ns
110 ns
80 ns
260 ns
130 ns
90 ns
60 ns
24 ns
20 ns
80 ns
40 ns
30 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
SYMBOL
MIN.
TYP.
MAX.
HEF4731B; HEF4731V
LSI
TYPICAL EXTRAPOLATION
FORMULA
132 ns
+
(0,26 ns/pF) C
L
47 ns
+
(0,16 ns/pF) C
L
34 ns
+
(0,11 ns/pF) C
L
138 ns
+
(0,45 ns/pF) C
L
56 ns
+
(0,19 ns/pF) C
L
39 ns
+
(0,13 ns/pF) C
L
10 ns
+
(0,40 ns/pF) C
L
3 ns
+
(0,18 ns/pF) C
L
3 ns
+
(0,13 ns/pF) C
L
8 ns
+
(0,65 ns/pF) C
L
5 ns
+
(0,30 ns/pF) C
L
5 ns
+
(0,20 ns/pF) C
L
see also waveforms Fig.4
Note: the maximum
power dissipation has
to be observed
Fig.4
Waveforms showing
minimum clock pulse
width, set-up and hold
times for D to CP.
Set-up and hold times
are shown as positive
values but may be
specified as negative
values.
January 1995
4
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