EEWORLDEEWORLDEEWORLD

Part Number

Search

51702-30402400CCLF

Description
Board Connector, 28 Contact(s), 4 Row(s), Male, Straight, Press Fit Terminal, LEAD FREE
CategoryThe connector    The connector   
File Size239KB,3 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Environmental Compliance  
Download Datasheet Parametric View All

51702-30402400CCLF Overview

Board Connector, 28 Contact(s), 4 Row(s), Male, Straight, Press Fit Terminal, LEAD FREE

51702-30402400CCLF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAmphenol
package instructionLEAD FREE
Reach Compliance Codecompli
Other featuresTERMINAL PITCH FOR POWER CONTACTS: 6.35 MM
Connector typeBOARD CONNECTOR
Contact to complete cooperationGOLD (30) OVER NICKEL (50)
Contact completed and terminatedGOLD (5) OVER NICKEL (50)
Contact point genderMALE
Contact materialCOPPER ALLOY
DIN complianceNO
Filter functionNO
IEC complianceNO
JESD-609 codee4
MIL complianceNO
Manufacturer's serial number51702
Mixed contactsYES
Installation methodSTRAIGHT
Installation typeBOARD
Number of rows loaded4
OptionsGENERAL PURPOSE
Terminal pitch2.54 mm
Termination typePRESS FIT
Total number of contacts28
UL Flammability Code94V-0
PDM: Rev:P
STATUS:
Released
Printed: Dec 20, 2010
.
EEWORLD University Hall----Live Replay: Detailed Explanation of Ultra-Low Power RSL10 Bluetooth SoC Development Board
Live replay: Detailed explanation of ultra-low power RSL10 Bluetooth SoC development board : https://training.eeworld.com.cn/course/6056...
hi5 Integrated technical exchanges
Is the larger the UPS power factor, the better?
For a long time, the issue of UPS power factor has been a focus of debate for both UPS suppliers and users : users claim to want UPS with a high power factor, and suppliers also say that the higher th...
frozenviolet MCU
I just started learning VHDL and I have some questions to ask you! Please help me.
I would like to ask you, why when my key0_state generates a falling edge, dout1, dout2, dout3 can all be assigned a value of 0, but when other key_states generate a falling edge, dout1, dout2, dout3 c...
jinghong21 FPGA/CPLD
[Help] Questions about 430 procedure??? Thank you
#includevoid main(void){WDTCTL=WDTPW+WDTHOLD;TACTL=TASSEL0+TACLT+MC0;CCTL0=CCIE;CCR0=16384;P3DIR|=BIT7;_EINT();while(1);//Excuse me, what is the use of this statement? Which statements are executed in...
烟头小徐 Microcontroller MCU
Help!!!
Hey guys, does anyone have the application circuit diagram of the ADG408 analog switch to complete the eight-choose-one function? Can you share it? I am a novice and I really don’t understand how it r...
小桥流水0201 PCB Design
XILINX SPARTAN-6 FPGA SP601 Evaluation Kit Available for a Limited Time
http://china.xilinx.com/products/devkits/EK-S6-SP601-G.htmSale price: $249!Provide industry information to facilitate colleagues...
eeleader FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 340  2265  2426  1399  2110  7  46  49  29  43 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号