CBTL04GP043
Dual 2 x 2 differential channel crossbar switch
Rev. 1.1 — 27 July 2015
Product data sheet
1. General description
The CBTL04GP043 is a high-performance 4-channel bidirectional crossbar switch
supporting both high speed and large swing signals. The high-speed differential signals
include PCIe-Gen3, USB3 and DisplayPort. The large swing signals include UART,
USB 2.0 and HDMI 1.4 signals.
This chip can be configured as pair straight through or cross to the output ports through
the CROSS signal. It can be placed under Low-power mode using the XSDN pin.
This crossbar switch supports wide common-mode voltage range from 0 V to V
DD
on all
input and output ports.
CBTL04GP043 is available in 2.00 mm
4.00 mm
0.5 mm XFBGA28 package with
0.5 mm pitch.
2. Features and benefits
4-channel, bidirectional crossbar switch
The input of the CROSS pin
CROSS is LOW for connecting input and output ports straight through
CROSS is HIGH for crossbar connection between input and output ports
When XSDN is LOW, the switch is in low-power sleep mode
Low ON-state resistance: 11
(typical)
Bandwidth: 8.5 GHz (typical) for V
IC
= 2.2 V
Low insertion loss:
1.5
dB at 2.5 GHz;
1
dB at 100 MHz
Low return loss:
20
dB at 2.5 GHz
Low off-state isolation:
16
dB at 2.5 GHz;
40
dB at 100 MHz
Low DDNEXT crosstalk:
20
dB at 2.5 GHz
V
IC
common-mode input voltage V
IC
: 0 V to V
DD
Differential input voltage V
ID
: 1.4 V (maximum)
Intra-pair skew: 5 ps (typical)
Supports power supply voltage range from 2.7 V to 3.5 V
Back current protection on all I/O pins of these switches
All channels support rail-to-rail input voltage
XFBGA28 2 mm
4 mm
0.5 mm package with 0.5 mm pitch
ESD: 2000 V HBM; 750 V CDM
Operating temperature range:
20 C
to +85
C
NXP Semiconductors
CBTL04GP043
Dual 2 x 2 differential channel crossbar switch
3. Ordering information
Table 1.
Ordering information
Topside
marking
GP43*
[1]
Package
Name
XFBGA28
Description
plastic, extremely thin fine-pitch ball grid array package;
28 balls; body 2.00
4.00
0.5 mm; 0.5 mm pitch
Version
SOT1356-1
Type number
CBTL04GP043EX
[1]
‘*’ changes based on date code.
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
CBTL04GP043EXJ
Package
Packing method
Minimum
order
quantity
7000
Temperature
Type number
CBTL04GP043EX
XFBGA28
Reel 13” Q1/T1
*standard mark SMD
T
amb
=
20 C
to +85
C
4. Block diagram
CBTL04GP043
A0_P
A0_N
A1_P
A1_N
B0_P
B0_N
B1_P
B1_N
C0_P
C0_N
C1_P
C1_N
D0_P
D0_N
D1_P
D1_N
CROSS
XSDN
aaa-012968
Fig 1.
Block diagram of CBTL04GP043
CBTL04GP043
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 27 July 2015
2 of 19
NXP Semiconductors
CBTL04GP043
Dual 2 x 2 differential channel crossbar switch
5. Pinning information
5.1 Pinning
ball A1
index area
1
A
A
B
B
C
C
D
D
E
E
F
G
H
G
Transparent top view
H
aaa-012969
CBTL04GP043EX
2
3
4
1
A1_P
A1_N
CROSS
n.c.
n.c.
V
SS
A0_P
A0_N
B0_P
B0_N
C0_P
C0_N
n.c.
n.c.
n.c.
n.c.
2
B1_P
B1_N
3
D1_P
D1_N
4
C1_P
C1_N
V
DD
n.c.
n.c.
XSDN
D0_P
D0_N
F
An empty cell indicates no ball
is populated at that grid point.
n.c. = ball present, but not internally connected.
aaa-013489
Transparent top view
a. Pin configuration
Fig 2.
Pin configuration for XFBGA28
b. Ball mapping
CBTL04GP043
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 27 July 2015
3 of 19
NXP Semiconductors
CBTL04GP043
Dual 2 x 2 differential channel crossbar switch
5.2 Pin description
Table 3.
Symbol
A1_P
A1_N
B1_P
B1_N
C1_P
C1_N
D1_P
D1_N
A0_P
A0_N
B0_P
B0_N
C0_P
C0_N
D0_P
D0_N
CROSS
Pin description
Pin
A1
B1
A2
B2
A4
B4
A3
B3
G1
H1
G2
H2
G3
H3
G4
H4
C1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CMOS
input
When CROSS = HIGH, selects cross function.
When CROSS = LOW, selects pass-through function.
CROSS input must be LOW for more than 500
s
during
start up time.
XSDN
F4
CMOS
input
When XSDN = HIGH, enables XBAR switches.
When XSDN = LOW, all switches are 3-stated.
Power supply range from 3.0 V to 3.5 V.
Supply ground (0 V).
Not connected. These balls should be connected to solid
ground plane on PCB to improve signal integrity.
Port D0
Port C0
Port B0
Port A0
Port D1
Port C1
Port B1
Description
Port A1
Data path signals
Control signals
Power supply
V
DD
V
SS
n.c.
C4
F1
D1, D2, D3,
D4, E1, E2,
E3, E4
power
ground
-
Ground connection
CBTL04GP043
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 27 July 2015
4 of 19
NXP Semiconductors
CBTL04GP043
Dual 2 x 2 differential channel crossbar switch
6. Functional description
Refer to
Figure 1 “Block diagram of CBTL04GP043”.
When CROSS input is LOW, Port 0 pins are connected to their respective Port 1 pins.
When CROSS input is HIGH, Port 0 A and B are crossed to Port 1 B and A,
Port 0 C and D are crossed to Port 1 D and C.
When XSDN input is HIGH, the crossbar switch is in normal operation mode. When XSDN
input is LOW, the crossbar switch is placed under high-impedance state.
Table 4.
Function table
XSDN = 0
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
high-Z
XSDN = 1,
CROSS = 0
A0_P
A0_N
B0_P
B0_N
C0_P
C0_N
D0_P
D0_N
XSDN = 1,
CROSS = 1
B0_P
B0_N
A0_P
A0_N
D0_P
D0_N
C0_P
C0_N
Port 1 connected to
Port 0
A1_P
A1_N
B1_P
B1_N
C1_P
C1_N
D1_P
D1_N
7. Power-up sequence
The CROSS pin must be LOW before start-up time has elapsed. After both V
DD
and
XSDN go HIGH for 500
s
(t
startup
time), CROSS input can be toggled to HIGH.
V
DD
XSDN
t
startup
CROSS
aaa-014237
Fig 3.
CROSS pin power-up sequence
CBTL04GP043
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 27 July 2015
5 of 19
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