813252CKI-02 datasheet, PDF - EEWORLD Datasheet

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813252CKI-02: DescriptionPLL Based Clock Driver, 813252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32; Categorylogic logic; File Size245KB，22 Pages; ManufacturerIDT (Integrated Device Technology)

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813252CKI-02 Overview

PLL Based Clock Driver, 813252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32

813252CKI-02 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFN
package instruction	5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32
Contacts	32
Reach Compliance Code	not_compliant
series	813252
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N32
JESD-609 code	e0
length	5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	2
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-EMITTER
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	5 mm
minfmax	312.5 MHz
Base Number Matches	1

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Jitter Attenuator & FemtoClock

Multiplier

ICS813252I-02

DATA SHEET

ENERAL

ESCRIPTION

The ICS813252I-02 is a PLL based synchronous multiplier

that is optimized for PDH or SONET to Ethernet clock jitter

attenuation and frequency translation. The device contains two

internal frequency multiplication stages that are cascaded in

series. The first stage is a VCXO PLL that is optimized to provide

reference clock jitter attenuation. The second stage is a

FemtoClock

frequency multiplier that provides the low jitter,

high frequency Ethernet output clock that easily meets Gigabit

and 10 Gigabit Ethernet jitter requirements. Pre-divider and

output divider multiplication ratios are selected using device

selection control pins. The multiplication ratios are optimized

to support most common clock rates used in PDH, SONET and

Ethernet applications. The VCXO requires the use of an

external, inexpensive pullable crystal. The VCXO uses external

passive loop filter components which allows configuration of

the PLL loop bandwidth and damping characteristics. The

device is packaged in a space-saving 32-VFQFN package and

supports industrial temperature range.

EATURES

•

Two LVPECL outputs

Each output supports independent frequency selection at

25MHz, 125MHz, 156.25MHz and 312.5MHz

•

Two differential inputs support the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

•

Accepts input frequencies from 8kHz to 155.52MHz including

8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,

125MHz and 155.52MHz

•

Attenuates the phase jitter of the input clock by using a low-

cost pullable fundamental mode VCXO crystal

•

VCXO PLL bandwidth can be optimized for jitter attenuation

and reference tracking

using external loop filter connection

•

FemtoClock frequency multiplier provides low jitter, high

frequency output

•

Absolute pull range: 50ppm

•

FemtoClock VCO frequency: 625MHz

•

RMS phase jitter @ 125MHz, using a 25MHz crystal

(10kHz – 20MHz): 1.3ps (maximum)

•

3.3V supply voltage

•

-40°C to 85°C ambient operating temperature

SSIGNMENT

XTAL_OUT

XTAL_IN

nCLK0

nCLK1

CLK0

CLK1

CCX

•

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

32 31 30 29 28 27 26 25

LF1

LF0

ISET

CLK_SEL

RESERVED

9 10 11 12 13 14 15 16

CCA

ODBSEL_1

ODBSEL_0

PDSEL_2

PDSEL_1

PDSEL_0

ODASEL_1

nQB

CCO

nQA

ODASEL_0

ICS813252I-02

32-Lead VFQFN

5mm x 5mm x 0.925 package body

K Package

Top View

ICS813252CKI-02 REVISION A AUGUST 25, 2010

Integrated Device Technology, Inc.

813252CKI-02 Related Products

	813252CKI-02	813252CKI-02T
Description	PLL Based Clock Driver, 813252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32	PLL Based Clock Driver, 813252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFN	QFN
package instruction	5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32	5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32
Contacts	32	32
Reach Compliance Code	not_compliant	not_compliant
series	813252	813252
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-XQCC-N32	S-XQCC-N32
JESD-609 code	e0	e0
length	5 mm	5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	32	32
Actual output times	2	2
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	OPEN-EMITTER	OPEN-EMITTER
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	225	225
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns	0.075 ns
Maximum seat height	1 mm	1 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	5 mm	5 mm
minfmax	312.5 MHz	312.5 MHz
Base Number Matches	1	1

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