DSC400-3343Q0001KI2T datasheet, PDF

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DSC400-3343Q0001KI2T: DescriptionOTHER CLOCK GENERATOR; CategoryThe embedded processor and controller Microcontrollers and processors; File Size454KB，15 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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DSC400-3343Q0001KI2T Overview

OTHER CLOCK GENERATOR

DSC400-3343Q0001KI2T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	HVQCCN,
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	CLK/CRYSTAL FREQ-NOM IS REPLACED WITH MEMS INTERNAL CLOCK
JESD-30 code	R-XQCC-N32
length	5 mm
Humidity sensitivity level	1
Number of terminals	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	460 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Filter level	AEC-Q100
Maximum seat height	0.9 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	2.25 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	3.2 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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DSC400

Configurable Four Output, Low Jitter Crystal-less™ Clock Generator

General Description

The DSC400 is a four output crystal-less™

clock generator. It utilizes Micrel’s proven

PureSilicon™ MEMS technology to provide

excellent

jitter

and

stability

while

incorporating additional device functionality.

The frequencies of the outputs can be

identical or independently derived from

common PLLs.

Each

output

may

configured

independently to support a single ended

LVCMOS interface or a differential interface.

Differential options include LVPECL, LVDS, or

HCSL.

The DSC400 provides two independent select

lines for choosing between two sets of pre-

configured frequencies per bank. It also has

two OE pins to allow for enabling and

disabling outputs.

The DSC400 is packaged in a 20-pin QFN

(5mm x 3.2mm) and is available in extended

commercial and

industrial

temperature

grades.

Features



Low RMS Phase Jitter: <1 ps (typ)



High Stability: ±25ppm, ±50ppm



Wide Temperature Range

Ext. commercial: -20°C to 70°C

Industrial: -40°C to 85°C



High Supply Noise Rejection: -50 dBc



Four format configurable outputs:

LVPECL, LVDS, HCSL, LVCMOS



Available Pin-Selectable frequency table

1 pin per bank for 2 frequency sets



Wide Freq. Range:

2.3 MHz – 460 MHz



20 QFN Footprint (5mm x 3.2mm)



Excellent Shock & Vibration Immunity

Qualified to MIL-STD-883



High Reliability

20x better MTF than quartz based devices



Wide Supply Range of 2.25 to 3.6 V



Lead Free & RoHS Compliant



AEC-Q100 Automotive Qualified

Block Diagram

Applications



Communications and Networks



Ethernet

1G, 10GBASE-T/KR/LR/SR, and FCoE



Storage Area Networks

SATA, SAS, Fibre Channel



Passive Optical Networks

EPON, 10G-EPON, GPON, 10G-PON



HD/SD/SDI Video & Surveillance



Automotive



Media and Video



Embedded and Industrial



_____________________________________________________________________________________________________________________________ _________________

DSC400

Page 1

DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator

Operational Description

The DSC400 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it

does not require an external crystal to operate; it relies on the integrated MEMS resonator that

interfaces with internal PLLs. This technology enhances performance and reliability by allowing

tighter frequency stability over a far wider temperature range. In addition, the higher resistance to

shock and vibration decreases the aging rate to allow for much improved product life in the system.

Inputs

There are 4 input signals in the device. Each has an internal (40kΩ) pull up to default the selection

to a high (1). Inputs can be controlled through hardware strapping method with a resistor to

ground to assert the input low (0). Inputs may also be controlled by other components’ GPIOs

In case more than one frequency set is desired, FSB1 and FSB2 are used for independently

selecting one of two sets per bank. FSB1 selects the pre-configured set on Bank1 (CLK0 and CLK3)

and FSB2 selects the pre-configured set on Bank2 (CLK1 and CLK2), as shown in table 2.

If there is a requirement to disable outputs, the inputs OE1 and OE2 are used in conjunction to

disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.

Table 1: Output Enable (OE) Selection Table

OE1

OE2

Bank1 (CLK0 & CLK3)

Hi-Z

Running

Bank2 (CLK1 & CLK2)

Hi-Z

Running

Hi-Z

Running

Outputs

The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to

allow for optimized noise isolation between the two banks. Each bank provides two synchronous

outputs generated by a common PLL:



Bank1 is composed of outputs CLK0 and CLK3

Bank2 is composed of outputs CLK1 and CLK2

Each output maybe pre-configured independently to be one of the following formats: LVCMOS,

LVDS, LVPECL or HCSL. In case the output is configured to be the single ended LVCMOS, the

frequency is generated on the true output (CLKx+) and the complement output (CLKx-) is shut off

in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential outputs and from

2.3MHz to 170MHz on LVCMOS outputs.

Power

VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different

supply voltage from the other as long as it is within the 2.25V to 3.6V range. Each VDD pin should

have a 0.1µF capacitor to filter high frequency noise. VSS is common to the entire device.

_____________________________________________________________________________________________________________________________ _________________

DSC400

Page 3

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