Aerospace Electronics
Advance Information
512K x 8 STATIC RAM—SOI
FEATURES
RADIATION
• Fabricated with RICMOS™ V Silicon On Insulator
(SOI) 0.35
µm
Process (L
eff
= 0.28
µm)
• Total Dose Hardness
≥3x10
5
rad(SiO
2
)
(Optional 1X10
6
rad(SiO
2
)
• Neutron Hardness
≥1x10
14
cm
-2
• Dynamic and Static Transient Upset Hardness
≥1x10
10
rad(Si)/s (3.3 V)
• Dose Rate Survivability
≥1x10
12
rad(Si)/s
• Soft Error Rate Upsets/bit-day
≤1x10
-10
(3.3 V)
• No Latchup
OTHER
• Read/Write Cycle Times
≤
20 ns, (3.3 V), 0 to 80°C
≤
25 ns, (3.3 V), -55 to 125°C
• Typical Operating Power
≤9.5
mW/MHz (3.3 V)
• Asynchronous Operation
• CMOS Compatible I/O
• Single Power Supply, 3.3 V
±
0.3 V
• Operating Range is -55°C to +125°C
• Package Options:
– 36-Lead Flat Pack
• Optional Low Power Sleep Mode
HX6408
GENERAL DESCRIPTION
The 512K x 8 Radiation Tolerant Static RAM is a high
performance 524,288 word x 8-bit static random access
memory with optional industry-standard functionality. It is
fabricated with Honeywell’s radiation hardened technol-
ogy, and is designed for use in low voltage systems
operating in radiation environments. The RAM operates
over the full military temperature range and requires only a
single 3.3 V
±
0.3V power supply. Power consumption is
typically less than 9.5 mW/MHz in operation, and less than
6 mW when de-selected.
Honeywell’s enhanced SOI RICMOS™ V (Radiation In-
sensitive CMOS) technology is radiation hardened through
the use of advanced and proprietary design, layout and
process hardening techniques. The RICMOS™ V low
power process is a SIMOX CMOS technology with a 80 Å
gate oxide and a minimum drawn feature size of 0.35
µm.
Additional features include tungsten via and contact plugs,
Honeywell’s proprietary SHARP planarization process
and a lightly doped drain (LDD) structure for improved short
channel reliability. A seven transistor (7T) memory cell is
used for superior single event upset hardening, while three
layer metal power busing and the low collection volume
SIMOX substrate provide improved dose rate hardening.
Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 238-1502 • http://www.ssec.honeywell.com
HX6408
FUNCTIONAL DIAGRAM
Address
Decoder
An
Memory
Array
8
NWE
DQ:0-7
Timing / Control
8
WE • CS
NSL
1 = enabled
Signal
#
Signal
NCS
NOE
NWE • CS
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
SIGNAL DEFINITIONS
A: 0-18
DQ: 0-7
NCS
Address input pins which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state. If this signal
is not used it must be connected to VSS.
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and NSL. If this signal is not used it must
be connected to VSS. This signal is asynchronous.
Not sleep, when at a high level allows normal operation. When at a low level NSL forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS and NOE input buffers. If this signal is not used it must be connected to VDD. This signal is
asynchronous. The HX6408 may be ordered without the sleep mode option and pin 36 is then a NC.
NWE
NOE
NSL
TRUTH TABLE
NCS
L
L
H
X
NS L
H
H
X
L
NWE
H
L
X
X
NO E
L
X
X
X
Mode
Read
Write
Deselected
Sleep
DQ
Data Out
Data In
High Z
High Z
X: VI=VIH or VIL,
NOE=H: High Z output state maintained for NCS=X,
CE=X, NWE=X
2
HX6408
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electrical
and timing performance parameters will remain within speci-
fications after rebound at VDD = 3.6 V and T =125°C ex-
trapolated to ten years of operation. Total dose hardness is
assured by wafer level testing of process monitor transistors
and RAM product using 10 KeV X-ray and Co60 radiation
sources. Transistor gate threshold shift correlations have
been made between 10 KeV X-rays applied at a dose rate of
1x10
5
rad(SiO
2
)/min at T = 25°C and gamma rays (Cobalt 60
source) to ensure that wafer level X-ray testing is consistent
with standard military radiation test environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient ioniz-
ing radiation pulse, up to the specified transient dose rate
upset specification, when applied under recommended
operating conditions. To ensure validity of all specified
performance parameters before, during, and after radiation
(timing degradation during transient pulse radiation is
≤10%),
it is suggested that stiffening capacitance be
placed near the package VDD and VSS, with a maximum
inductance between the package (chip) and stiffening ca-
pacitance of 0.7 nH per part. If there are no operate-
through or valid stored data requirements, typical circuit
board mounted de-coupling capacitors are recommended.
The SRAM will meet any functional or electrical specifica-
The SRAM is capable of meeting the specified Soft Error
Rate (SER), under recommended operating conditions.
This hardness level is defined by the Adams 90% worst
case cosmic ray environment for geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under recom-
mended operating conditions. Fabrication with the SIMOX
substrate material provides oxide isolation between adja-
cent PMOS and NMOS transistors and eliminates any
potential SCR latchup structures. Sufficient transistor body
tie connections to the p- and n-channel substrates are
made to ensure no source/drain snapback occurs.
tion after exposure to a radiation pulse up to the
transientdose rate survivability specification, when ap-
plied under recommended operating conditions. Note
that the current conducted during the pulse by the RAM
inputs, outputs, and power supply may significantly ex-
ceed the normal operating levels. The application design
must accommodate these effects.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This as-
sumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
RADIATION HARDNESS RATINGS (1)
Parameter
Total Dose
Transient Dose Rate Upset
Transient Dose Rate Survivability
Soft Error Rate
Neutron Fluence
Limits (2)
≥3x10
5
(Optional 1X10
6
)
≥1x10
10
≥1x10
12
<1x10
-10
≥1x10
14
Units
rad(SiO
2
)
rad(Si)/s
rad(Si)/s
upsets/bit-day
N/cm
2
Test Conditions
T
A
=25°C
Pulse width
≤50
ns
VDD>3.6V, TA=25°C
Pulse width
≤50
ns, X-ray,
VDD=3.6 V, T
A
=25°C
T
A
=85°C, Adams 90%
worst case environment
1 MeV equivalent energy,
Unbiased, T
A
=25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=3.0 V to 3.6 V, TA=-55°C to 125°C.
3
HX6408
ABSOLUTE MAXIMUM RATINGS
(1)
Rating
Symbol
VDD
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
Parameter
Supply Voltage Range (2)
Voltage on Any Pin (2)
Storage Temperature (Zero Bias)
Soldering Temperature (5 Seconds)
Maximum Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage
Thermal Resistance (Jct-to-Case)
Junction Temperature
36 Pin FP
2000
2
Min
-0.5
-0.5
-65
Max
4.6
VDD+0.5
150
270
2
25
Units
V
V
°C
°C
W
mA
V
°C/W
°C
Θ
JC
TJ
175
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Symbol
VDD
TA
VPIN
Parameter
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
Min
3.0
-55
-0.3
Typ
3.3
25
Max
3.6
125
VDD+0.3
Units
V
°C
V
CAPACITANCE
(1)
Symbol
CI
CO
Parameter
Input Capacitance
Output Capacitance
Typical
(1)
Worst Case
Min
Max
7
9
Units
pF
pF
Test Conditions
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Symbol
VDR
IDR
Parameter
Data Retention Voltage
Data Retention Current
Typical
(1)
Worst Case
(2)
Units
Min
2.25
1
Max
V
mA
NCS=VDR
VI=VDR or VSS
NCS=VDD=VDR
VI=VDR or VSS
Test Conditions
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.
4
HX6408
DC ELECTRICAL CHARACTERISTICS
Worst Case
(1)
Symbol
Parameter
Min
IDDSB
IDDSL
Static Supply Current
Static Supply Current with NSL Low
Max
5
5
3
3
1
-5
-10
5
10
0.3xV
DD
Units
Test Conditions
mA
mA
mA/MHz
mA/MHz
mA
µA
µA
V
V
VDD=max, Iout=0mA, Inputs Stable
VDD=max, Iout=0mA, f=fmax
VDD=max, Iout-0mA, f=1MHz
NSL=VIH, NCS=VIL (1)
VDD=max, Iout-0mA, f=1MHz)
NSL=VIH, NCS=VIL (1)
VDD=max, Iout-0mA, f=1MHz
NSL=NCS=VIH (2)
Vss VI VDD
Vss VIO VDD Output = high Z
VDD=3.0 V
VDD=3.6 V
VDD=3.0 V, IOL = 8mA
VDD=3.0V, IOH = 4mA
IDDOPW Dynamic Supply Current, Selected (Write)
IDDOPR
IDDOP
II
IOZ
VIL
VIH
VOL
VOH
Dynamic Supply Current, Selected (Read)
Dynamic Supply Current, Deselected
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
2.4
0.7xV
DD
0.4
V
V
(1) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55°C to +125°C, post total dose at 25°C.
(2) All inputs switching. DC average current.
2.2 V
Vref1
249Ω
DUT
output
Vref2
+
-
Valid high
output
+
-
Valid low
output
CL >50 pF*
*CL = 5 pF for TWLQZ, TSHQZ, TPLQZ, and TGHQZ
Tester Equivalent Load Circuit
5
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