NXP Semiconductors
Data Sheet: Technical Data
Document Number S32R372
Rev. 4, 08/2018
S32R372 Data Sheet
Features
• Dual issue computation cores: Power Architecture®
e200z7 32-bit CPU
• 1.3 MB on-chip code flash memory (FMC flash
memory) with ECC
• 1 MB on-chip SRAM with ECC
• RADAR processing
– Signal Processing Toolbox (SPT) for RADAR signal
processing acceleration
– Cross Triggering Engine (CTE) for precise timing
generation and triggering
– MIPICSI2 interface to connect external RADAR RX
ADCs
• Memory protection
– Each core memory protection unit provides 24
entries
– Data and instruction bus system memory protection
unit (SMPU) with 16 region descriptors each
– Register protection
• Clock generation
– 40 MHz external crystal (XOSC)
– 16 MHz Internal oscillator (IRCOSC)
– Dual system PLL with one frequency modulated
phase-locked loop (FMPLL)
– Low-jitter PLL
• Functional safety
– Enables ASIL-B applications
– Fault Collection and Control Unit (FCCU) for fault
collection and fault handling
– Memory Error Management Unit (MEMU) for
memory error management
– Safe eDMA controller
– Self-Test Control Unit (STCU2)
– Error Injection Module (EIM)
– On-chip voltage monitoring
– Clock Monitor Unit (CMU)
S32R372
• Security
– Cryptographic Security Engine (CSE2)
– Supports censorship and life-cycle management
• Timers
– Two Periodic Interval Timers (PIT) with 32-bit
counter resolution
– Two System Timer Module (STM)
– Two Software Watchdog Timers (SWT)
– One eTimer module with 6 channels each
– One FlexPWM module for 12 PWM signals
• Communication interfaces
– Two Serial Peripheral interface (SPI) modules
– One LINFlexD module
– Two inter-IC communication interface (I2C)
modules
– Two FlexCAN modules supporting CAN FD with
configurable buffers
• Debug functionality
– 4-pin JTAG interface and Nexus/Aurora interface
for serial high-speed tracing
– e200z7 core: Nexus development interface (NDI)
per IEEE-ISTO 5001-2012 Class 3+
• Two analog-to-digital converters (SAR ADC)
– Each ADC supports up to 16 input channels
– Cross Trigger Unit (CTU)
• On-chip voltage DC/DC regulator for core supply
generation (VREG)
• Two Temperature Sensors (TSENS)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1
Introduction........................................................................................ 3
1.1
1.2
1.3
2
Chip comparison..................................................................... 3
Feature list............................................................................... 4
Block diagram......................................................................... 8
8.3
8.4
8.5
8.6
Flash memory module life specifications................................31
Data retention vs program/erase cycles...................................32
Flash memory AC timing specifications.................................32
Flash memory read wait-state and address-pipeline control
settings.....................................................................................33
9
Communication modules................................................................... 34
9.1
9.2
9.3
SPI timing specifications.........................................................34
LINFlexD timing specifications..............................................39
I2C timing .............................................................................. 39
Ordering parts.....................................................................................9
2.1
Determining valid orderable parts...........................................9
3
Part identification............................................................................... 9
3.1
3.2
3.3
Description.............................................................................. 9
Format..................................................................................... 9
Fields....................................................................................... 9
10 Debug modules...................................................................................40
10.1 JTAG/CJTAG interface timing .............................................. 40
10.2 Nexus Aurora debug port timing.............................................43
11 WKPU/NMI timing specifications.....................................................44
12 External interrupt timing (IRQ pin)................................................... 45
13 Temperature sensor electrical characteristics.....................................45
14 Radar module..................................................................................... 46
14.1 MIPICSI2 D-PHY electrical and timing specifications.......... 46
14.2 MIPICSI2 disclaimer...............................................................49
15 Thermal characteristics...................................................................... 50
15.1 General notes for specifications at maximum junction
temperature..............................................................................51
15.2 References............................................................................... 53
16 Packaging........................................................................................... 53
17 Reset sequence................................................................................... 54
17.1 Reset sequence duration.......................................................... 54
17.2 Reset sequence description......................................................54
18 Power sequencing requirements.........................................................57
19 Package pinouts and signal descriptions............................................ 58
20 Release Notes..................................................................................... 59
4
General............................................................................................... 11
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Introduction............................................................................. 11
Absolute maximum ratings..................................................... 11
Operating conditions............................................................... 13
Supply current characteristics................................................. 14
Voltage regulator electrical characteristics............................. 15
Electromagnetic Compatibility (EMC) specifications............ 19
Electrostatic discharge (ESD) characteristics......................... 19
5
I/O Parameters....................................................................................20
5.1
5.2
5.3
5.4
I/O pad DC electrical characteristics ......................................20
I/O pad AC specifications....................................................... 21
Aurora LVDS driver electrical characteristics........................ 22
Reset pad electrical characteristics..........................................22
6
Peripheral operating requirements and behaviors.............................. 24
6.1
Clocks and PLL Specifications............................................... 24
7
Analog................................................................................................ 27
7.1
ADC electrical characteristics.................................................27
8
Memory modules............................................................................... 29
8.1
8.2
Flash memory program and erase specifications.................... 29
Flash memory Array Integrity and Margin Read
specifications...........................................................................30
S32R372 Data Sheet, Rev. 4, 08/2018
2
NXP Semiconductors
Introduction
1 Introduction
1.1 Chip comparison
The following table provides a comparison and their proposed features of three devices
S32R372, S32R274 and MPC5775K . For full details of all of the family derivatives
please contact your marketing representative.
Table 1. S32R372 Chip comparison table
Feature
CPUs
SIMD
Maximum Operating
Frequency
Flash
EEPROM support
RAM
ECC
MPU
eDMA
Control ADC
1
2x 12-bit SAR ADC, 1
MSps input mux for 16
external channels
-
1x v2.5
-
1x
2x
2x
S32R372
2x e200z7260
SPE2 + EFP2 (both
z7)
240 MHz
1.3 MB with ECC
32K (emulation)
1 MB with ECC
S32R274
2x e200z7260
e200z420 lock-step
SPE2 + EFP2 (both z7)
240 MHz (z7) 180 MHz (z4)
2 MB with ECC
64K (emulation)
1.5 MB with ECC
end-to-end
CoreMPU: 24 entries per core
SystemMPU: 2x16 entries
safe eDMA with 32 channels, 64 triggers
2x 12-bit SAR ADC, 1 MSps input
mux for 16 external channels
4x 12-bit
ΣΔ
ADC, 10 MSps
1x v2
1x
1x
1x
3x
3x
2x
2x
1x
1x
2x FlexCAN-FD
2x
1x
3x FlexCAN including 2x FlexCAN-
FD
2x
Table continues on the next page...
4x
4x FlexCAN + 1x MCAN-FD
4x
1x
2x
3x
3x
4x 12bit SAR ADC, 1 MSps,
input mux for 37 external
channels
8x 12-bit
ΣΔ
ADC, 10 MSps
1x v1
SPE2 + EFP2 (both z7)
266 MHz (z7) 133 MHz (z4)
4 MB with ECC
96K (emulation)
1.5 MB with ECC
MPC5775K
RADAR ADC
SPT
CTE
1
WGM
CTU
SWT
STM
PIT
CRC
SEMA42
LINFlexD
2
FlexCAN
SPI
1
S32R372 Data Sheet, Rev. 4, 08/2018
NXP Semiconductors
3
Introduction
Table 1. S32R372 Chip comparison table (continued)
Feature
I
2
C
,
3
Zipwire
FlexRay
Ethernet
FlexPWM
1
eTimer
1
External ADC interface
IRCOSC
XOSC
FMPLL
DAC
SIUL2
1
BAM
INTC
SSCM
FCCU/FOSU
MEMU
STCU2
CSE
PASS
TDM
MC_ME
MC_CGM
MC_RGM
TSENS
Debug
Safety Level
Temp. Range (Tj)
ISO26262 SEooC
ASIL-B
1x
1x
1x
1x
1x
1x
1x
1x
1x
2x
JTAGC, JTAGM, CJTAG, with class3+Nexus, Aurora only
ISO26262 SEooC ASIL-B to ASIL-D
-40 to +150˚C
-
S32R372
2x
-
-
-
1x, 12 PWM channels
1x, 6 channels
1x 2 lanes MIPICSI2
Rx, 1Gbps/lane
S32R274
2x
1x LFAST+SIPI, 320MHz
1x dual channel
10/100 and >100 Mbps, RMII/MII/
RGMII I/F, AVB support
1x, 12 PWM channels
2x, 6 channels each
1x 4 lanes MIPICSI2 Rx, 1Gbps/lane
16 MHz
40 MHz
dual system PLL, 1x FM modulated
1x 12-bit 10MSps
1x
1x
1x
1x
1x
1x
1x
-
-
-
1x 12-bit 2MSps
10/100Mbps, RMII/MII I/F,
AVB support
2x, 12 PWM channels each
3x, 6channels each
1x PDI (16-bit data, clock,
sync)
MPC5775K
3x
1. This chip offers limited functionality with 10 mm x 10 mm outline. For details see
Feature list
2. Available only with 14 mm x 14 mm outline for this chip.
3. Single I
2
C available with 10 mm x 10 mm outline for this chip.
1.2 Feature list
On-chip modules available within the device include the following features:
• Two computation cores: Power Architecture e200z7 32-bit CPU
S32R372 Data Sheet, Rev. 4, 08/2018
4
NXP Semiconductors
Introduction
Dual issue: up to two instructions per clock cycle
Harvard architecture with 64-bit bus for data instructions
16 KB instruction cache and 16 KB data cache
64 KB data local memory
• with background load/store: backdoor access
• 0-wait state for all read and 32/64-bit write accesses
• Low number of wait states for backdoor accesses
• Support for decorated storage
• Using variable length encoding (VLE) for higher code density
• 4-way integer processing unit (SPE2)
• 2-way single-precision Floating Point Unit (EFP2)
• 1.3 MB on-chip code flash (FMC flash) with ECC
• Three ports (one per CPU, one for RADAR processing) shared between code
and data flash with 4 × 256 bit buffer for code and data flash including prefetch
functions
• Data flash is part of the code flash module
• Including 32 KB EEPROM emulation
• 1 MB on-chip SRAM with ECC
• Decorated memory controller to support atomic read-modify-write operations
• Single- and double-bit error visibility is supported
• Four ports (one per CPU, one for RADAR processing, one for all other) and up
to 6 banks allow simultaneous accesses from different masters to different banks
• RADAR processing
• Signal Processing Toolbox (SPT) for RADAR signal processing acceleration
• Cross Triggering Engine (CTE) for precise timing generation and triggering
1
• MIPICSI2 interface to connect external ADCs
• Two data lanes, with up to 1 GB/s per lane and in total
• One clock lane
• Memory protection
• Each core memory protection unit provides 24 entries
• Data and instruction bus system memory protection Unit (SMPU) with 16 region
descriptors each
• Register protection
• Clock generation
• 40 MHz external crystal (XOSC)
• 16 MHz Internal oscillator (IRCOSC)
• Dual system PLL with one frequency modulated phase-locked loop (FMPLL)
• Low-jitter SDPLL
• Functional safety
1.
This chip offers limited functionality with 10 mm x 10 mm outline.
•
•
•
•
S32R372 Data Sheet, Rev. 4, 08/2018
NXP Semiconductors
5
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