Semiconductor
NOT
October 1998
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MEN e HI580
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DES
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HI5804
12-Bit, 5 MSPS A/D Converter
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MSPS
• Low Power
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . 100MHz
Description
The HI5804 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Harris’ HBC10 BiCMOS process. It is
designed for high speed, high resolution applications where
wide bandwidth and low power consumption are essential.
The HI5804 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5804 has excellent dynamic
performance while consuming 300mW power at 5 MSPS.
[ /Title (HI5804)
• Low Distortion
/Subject (12-Bit, 5 MSPS A/D Converter)
The 100MHz full power input bandwidth is ideal for
• Internal
()
/Author
Reference
communication
systems
and
document
scanner
• TTL/CMOS
(Harris Semiconductor, A/D, Analog to Dig-
/Keywords
Compatible Digital I/O
applications. Data output latches are provided which present
ital Converter, Narrow
. .
Band,
.
Communications,
5V
valid data to the output bus with a latency of 3 clock cycles.
• Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . 3V to
High
The
Speed Converters, High Resolution Converters, Basesta-
digital outputs have a separate supply pin which can be
powered from a 3.0V to 5.0V supply.
Applications
tion, Cellular)
/Creator ()
Data Acquisition Systems
Ordering Information
• High Speed
/DOCINFO pdfmark
• Digital IF Communication Systems
• Document and Film Scanners
PART
NUMBER
SAMPLE
RATE
5 MSPS
TEMP.
RANGE (
o
C)
0 to 70
25
PACKAGE
28 Ld SOIC
PKG.
NO.
[ /PageMode /UseOutlines
• Medical Imaging
/DOCVIEW pdfmark
• Radar Signal Analysis
HI5804KCB
HI5804EVAL
M28.3
Evaluation Board
• Vibration/Waveform Spectrum Analysis
• Digital Servo Loop Control
• Reference Literature
- AN9214 Using Harris High Speed Converters
- AN9647 Using the HI5804 Evaluation Board
Pinout
HI5804
(SOIC)
TOP VIEW
CLK 1
DV
CC1
2
DGND1 3
DV
CC1
4
DGND1 5
AV
CC
6
28 D0
27 D1
26 D2
25 D3
24 D4
23 D5
22
DV
CC2
AGND 7
V
IN
+ 8
V
IN
- 9
V
DC
10
V
ROUT
11
V
RIN
12
AGND 13
AV
CC
14
21 DGND2
20 D6
19 D7
18 D8
17 D9
16 D10
15 D11
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1998
File Number
4026.5
1
HI5804
Functional Block Diagram
V
DC
V
IN
-
V
IN
+
S/H
STAGE 1
DV
CC2
BIAS
CLOCK
REF
CLK
V
ROUT
V
RIN
4-BIT
FLASH
+
∑
X8
4-BIT
DAC
-
D11 (MSB)
D10
DIGITAL DELAY
AND
DIGITAL ERROR CORRECTION
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
STAGE 3
4-BIT
FLASH
+
∑
X8
4-BIT
DAC
-
STAGE 4
4-BIT
FLASH
DGND2
AV
CC
AGND
DV
CC1
DGND1
Typical Application Schematic
(LSB) (28) D0
(27) D1
(26) D2
V
ROUT
(11)
(25) D3
V
RIN
(12)
(24) D4
AGND (7)
(23) D5
AGND (13)
(20) D6
DGND1 (3)
(19) D7
DGND1 (5)
(18) D8
DGND2 (21)
(17) D9
(16) D10
(MSB) (15) D11
V
IN
+
V
IN
+ (8)
V
DC
(10)
V
IN
-
CLOCK
V
IN
- (9)
CLK (1)
(4) DV
CC1
(2) DV
CC1
(22) DV
CC2
0.1µF
(6) AV
CC
(14) AV
CC
HI5804
0.1µF
+
10µF
+
10µF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
DGND
AGND
BNC
2
HI5804
Absolute Maximum Ratings
Supply Voltage, AV
CC
or DV
CC
to A
GND
or D
GND
. . . . . . . . . . . +6.0V
D
GND
to A
GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D
GND
to DV
CC
Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A
GND
to AV
CC
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
HI5804KCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, HI5804KCB . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
CC
= DV
CC1
= DV
CC2
= +5.0V, f
S
= 5 MSPS at 50% Duty Cycle, V
RIN
= 3.5V, C
L
= 10pF,
T
A
= 25
o
C, Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
Offset Error, V
OS
Full Scale Error, FSE
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
Maximum Conversion Rate
Effective Number of Bits, ENOB
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
-
=
-------------------------------------------------------------
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
-
=
------------------------------
RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
Transient Response
Over-Voltage Recovery
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input Range
(V
IN
+ - V
IN
-)
Maximum Peak-to-Peak Single-Ended Analog Input Range
Analog Input Resistance, R
IN
Analog Input Capacitance, C
IN
Analog Input Bias Current, I
B
+ or I
B
-
Differential Analog Input Bias Current I
B DIFF
= (I
B
+ - I
B
-)
Full Power Input Bandwidth, FPBW
Analog Input Common Mode Voltage (V
IN
+ + V
IN
-)/2
12
f
IN
= DC
f
IN
= DC
f
IN
= DC
f
IN
= DC
No Missing Codes
No Missing Codes
f
IN
= 1MHz
f
IN
= 1MHz
-
-
-
-
-
±2
±0.5
12
24
-
-
±1
-
-
Bits
LSB
LSB
LSB
LSB
-
-
-
-
0.5
5
10.3
64
-
-
-
-
MSPS
MSPS
Bits
dB
f
IN
= 1MHz
-
65
-
dB
f
IN
= 1MHz
f
IN
= 1MHz
f
IN
= 1MHz
f
IN
= 1MHz
f
1
= 1MHz, f
2
= 1.02MHz
0.2V Overdrive
-
-
-
-
-
-
-
-70
-73
-73
73
-66
1
2
±2.0
4.0
-
10
-
±0.5
100
2.3
-
dBc
dBc
-
-
-
-
-
dBc
dBc
dBc
Cycle
Cycle
-
-
(Notes 2, 3)
1
-
-10
-
-
Differential Mode (Note 2)
1
-
-
V
V
MΩ
pF
µA
µA
MHz
V
-
-
+10
-
-
4
3
HI5804
Electrical Specifications
AV
CC
= DV
CC1
= DV
CC2
= +5.0V, f
S
= 5 MSPS at 50% Duty Cycle, V
RIN
= 3.5V, C
L
= 10pF,
T
A
= 25
o
C, Unless Otherwise Specified
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, V
ROUT
Reference Output Current
REFERENCE INPUT
Total Reference Resistance, R
L
Reference Current
DC BIAS VOLTAGE
DC Bias Voltage Output, V
DC
Max Output Current (Not to Exceed)
DIGITAL INPUT, CLK
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic High Current, I
IH
Input Logic Low Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS, D0-D11
Output Logic Sink Current, I
OL
Output Logic Source Current, I
OH
Output Capacitance, C
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
AP
Aperture Jitter, t
AJ
Data Output Delay, t
OD
Data Output Hold, t
H
Data Latency, t
LAT
Clock Pulse Width (Low)
Clock Pulse width (High)
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AV
CC
Digital Supply Voltage, DV
CC1
Digital Output Supply Voltage, DV
CC2
Total Supply Current, I
CC
Analog Supply Current, AI
CC
Digital Supply Current, DI
CC1
Digital Output Supply Current, DI
CC2
Power Dissipation
Offset Error Sensitivity,
∆V
OS
Gain Error Sensitivity,
∆FSE
NOTES:
-
-
3.5
-
-
1
V
mA
-
-
7.8
450
-
-
kΩ
µA
-
-
2.3
-
-
1
V
mA
2.0
-
V
CLK
= 5V
V
CLK
= 0V
-
-
-
-
-
-
-
7
-
0.8
10.0
10.0
-
V
V
µA
µA
pF
V
O
= 0.4V (Note 2)
DV
CC2
= 3.0V, V
O
= 0.4V
V
O
= 2.4V (Note 2)
DV
CC2
= 3.0V, V
O
= 2.4V
1.6
-
-0.2
-
-
-
1.6
-
-0.2
5
-
-
-
-
-
mA
mA
mA
mA
pF
-
-
-
-
For a Valid Sample (Note 2)
5MHz Clock
5MHz Clock
-
90
90
5
5
8
8
-
100
100
-
-
-
-
3
110
110
ns
ps
RMS
ns
ns
Cycle
ns
ns
4.75
4.75
2.85
V
IN
+ - V
IN
- = 2V
V
IN
+ - V
IN
- = 2V
V
IN
+ - V
IN
- = 2V
V
IN
+ - V
IN
- = 2V
V
IN
+ - V
IN
- = 2V
AV
CC
or DV
CC
= 5V
±5%
AV
CC
or DV
CC
= 5V
±5%
-
-
-
-
-
-
-
5.0
5.0
-
60
46
13
1
300
±
16
±
16
5.25
5.25
5.25
-
-
-
-
-
-
-
V
V
V
mA
mA
mA
mA
mW
LSB
LSB
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
4
HI5804
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
S
N - 1
H
N - 1
S
N
H
N
S
N + 1
H
N + 1
S
N + 2
H
N + 2
S
N + 3
H
N + 3
S
N + 4
H
N + 4
S
N+5
H
N + 5
S
N + 6
H
N + 6
INPUT
S/H
1ST
STAGE
B
1, N - 1
B
1, N
B
1, N + 1
B
1, N + 2
B
1, N + 3
B
1, N + 4
B
1, N + 5
2ND
STAGE
B
2, N - 2
B
2, N - 1
B
2, N
B
2, N + 1
B
2, N + 2
B
2, N + 3
B
2, N + 4
3RD
STAGE
4TH
STAGE
B
3, N - 2
B
3, N - 1
B
3, N
B
3, N + 1
B
3, N + 2
B
3, N + 3
B
3, N + 4
B
4, N - 3
B
4, N - 2
B
4, N - 1
B
4, N
B
4, N + 1
B
4, N + 2
B
4, N + 3
DATA
OUTPUT
D
N - 3
D
N - 2
t
LAT
D
N - 1
D
N
D
N + 1
D
N + 2
D
N + 3
NOTES:
4. S
N
: N-th sampling period.
5. H
N
: N-th holding period.
6. B
M
,
N
: M-th stage digital output corresponding to N-th sampled input.D
N
:
Final data output corresponding to N-th sampled input.
FIGURE 1. HI5804 INTERNAL CIRCUIT TIMING
ANALOG
INPUT
t
AP
t
AJ
CLOCK
INPUT
1.5V
1.5V
t
OD
t
H
2.0V
DATA N-1
0.8V
DATA N
DATA
OUTPUT
FIGURE 2. INPUT-TO-OUTPUT TIMING
5
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