IDT74LVCH162823A
3.3V CMOS 18-BIT BUS INTERFACE REGISTER, 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
BUS INTERFACE REGISTER
WITH 5 VOLT TOLERANT I/O
AND BUS-HOLD
FEATURES:
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
– Extended commercial range of -40°C to +85°C
– V
CC
= 3.3V ±0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– CMOS power levels (0.4µ W typ. static)
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVCH162823A:
– Balanced Output Drivers: ±12mA
– Low Switching Noise
–
–
IDT74LVCH162823A
DESCRIPTION:
The LVCH162823A 18-bit bus interface register is built using advanced
dual metal CMOS technology. This high-speed, low-power register with
clock enable (CLKEN) and clear (CLR) controls is ideal for parity bus
interfacing in high-performance synchronous systems. The control inputs
are organized to operate the device as two 9-bit registers or one 18-bit
register. Flow-through organization of signal pins simplifies layput. All inputs
are designed with hysteresis for improved noise margin.
All pins of the LVCH162823A can be driven from either 3.3V or 5V
devices. This feature allows the use of this device as a translator in a mixed
3.3V/5V supply system.
The LVCH162823A has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been developed to drive ±12mA at the designated threshold
levels.
The LVCH162823A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
CLR
1
CLK
1
CLKEN
2
1
56
55
27
2
OE
2
CLR
2
CLK
2
CLKEN
28
29
30
R
R
R
3
R
C
C
C
C
D
D
1
D
1
54
1
Q
1
2
D
1
42
D
D
15
2
Q
1
TO EIGHT OTHER CHANNELS
TO EIGHT OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4683/-
IDT74LVCH162823A
3.3V CMOS 18-BIT BUS INTERFACE REGISTER, 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
CLR
1
OE
1
Q
1
ABSOLUTE MAXIMUM RATINGS
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
CLK
1
CLKEN
1
D
1
(1)
Unit
V
°C
mA
mA
mA
LVC Link
1
2
3
4
5
6
7
8
9
10
11
SO56-1
12 SO56-2
13 SO56-3
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
GND
1
Q
2
1
Q
3
GND
1
D
2
1
D
3
V
CC
1
Q
4
1
Q
5
1
Q
6
V
CC
1
D
4
1
D
5
1
D
6
GND
1
Q
7
1
Q
8
1
Q
9
2
Q
1
2
Q
2
2
Q
3
GND
1
D
7
1
D
8
1
D
9
2
D
1
2
D
2
2
D
3
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
LVC Link
GND
2
Q
4
2
Q
5
2
Q
6
GND
2
D
4
2
D
5
2
D
6
V
CC
2
Q
7
2
Q
8
V
CC
2
D
7
2
D
8
NOTE:
1. As applicable to the device type.
GND
2
Q
9
2
OE
2
CLR
GND
2
D
9
2
CLKEN
2
CLK
FUNCTION TABLE
Inputs
xOE
H
H
L
H
xCLR
X
L
L
H
H
H
H
H
H
xCLKEN
X
X
X
H
H
L
L
L
L
xCLK
X
X
X
X
X
(1)
Outputs
xDx
X
X
X
X
X
L
H
L
H
xQx
Z
Z
L
Z
Q
0
Z
Z
L
H
Load
Hold
Function
High Z
Clear
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xDx
xCLK
xCLKEN
xCLR
xOE
xQx
Description
Data Inputs
(1)
L
H
H
L
L
Clock Inputs
Clock Enable Inputs (Active LOW)
Asynchronous Clear Inputs
(Active LOW)
Output Enable Inputs (Active LOW)
3-State Outputs
↑
↑
↑
↑
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs,
outputs, or I/Os.
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH Transition
Q
0
= Level of Q before the indicated steady-state input conditions
were established.
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVCH162823A
3.3V CMOS 18-BIT BUS INTERFACE REGISTER, 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40
O
C to +85
O
C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
3.6
≤
V
IN
≤
5.5V
(2)
Quiescent Power Supply
Current Variation
One input at V
CC
- 0.6V
other inputs at V
CC
or GND
—
—
—
—
—
—
—
– 0.7
100
—
—
—
±50
– 1.2
—
10
10
500
µA
LVC Link
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
Unit
V
V
µA
µA
µA
V
mV
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
LVC Link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
—
—
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74LVCH162823A
3.3V CMOS 18-BIT BUS INTERFACE REGISTER, 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
V
CC
= 2.7V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
LVC Link
Unit
V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V
±
0.3V, TA = 25°C
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
—
—
Unit
pF
pF
4
IDT74LVCH162823A
3.3V CMOS 18-BIT BUS INTERFACE REGISTER, 5 VOLT I/O
EXTENDED COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V
Symbol
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
t
W
t
REM
t
SK
(o)
Parameter
Propagation Delay
xCLK to xQx
Propagation Delay
xCLR to xQx
Output Enable Time
xOE to xQx
Output Disable Time
xOE to xQx
Set-up Time HIGH or LOW
xDx to xCLK
Hold Time HIGH or LOW
xDx to xCLK
Set-up Time HIGH or LOW
xCLKEN to xCLK
Hold Time HIGH or LOW
xCLKEN to xCLK
xCLK Pulse Width
HIGH or LOW
xCLR Pulse Width LOW
Recovery Time xCLR to xCLK
Output Skew
(2)
Min
1.5
1.5
1.5
1.5
3
1.5
3.5
1.5
7
6
6
—
Max
10
12
11
10
—
—
—
—
—
—
—
—
Min
1.5
1.5
1.5
1.5
3
0
3.5
0
6
6
6
—
V
CC
= 3.3V±0.3V
Max
6
8
7
6.5
—
—
—
—
—
—
—
500
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
Embedded System
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