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852911AVILFT

Description
PLCC-28, Reel
Categorylogic    logic   
File Size329KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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852911AVILFT Overview

PLCC-28, Reel

852911AVILFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codePLCC
package instructionLCC-28
Contacts28
Manufacturer packaging codePLG28
Reach Compliance Codecompliant
ECCN codeEAR99
series852911
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-PQCC-J28
JESD-609 codee3
length11.505 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals28
Actual output times9
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC28,.5SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup1.7 ns
propagation delay (tpd)1.7 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.1 ns
Maximum seat height4.57 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.505 mm
minfmax500 MHz
Base Number Matches1
Low Skew, 1-to-9
Differential-to-HSTL Fanout Buffer
Data Sheet
852911I
G
ENERAL
D
ESCRIPTION
The 852911I is a low skew, 1-to-9 Differential-to-HSTL Fanout
Buffer. The 852911I has two selectable clock inputs which can
accept most differential input levels.
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the 852911I ideal for today’s most
advanced applications, such as IA64 and static RAMs.
F
EATURES
9 HSTL outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
HSTL_CLK, nHSTL_CLK pair can accept the following dif-
ferential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
PECL_CLK, nPECL_CLK supports the following input
types:
LVPECL, CML, SSTL
Maximum output frequency: 500MHz
Output skew: 100ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 1.7ns (maximum)
V
OH
= 1.4V (maximum)
3.3V core, 1.6V to 3.6V output supply range
-40°C to 85°C ambient operating temperature
B
LOCK
D
IAGRAM
HSTL_CLK
nHSTL_CLK
PECL_CLK
nPECL_CLK
CLK_SEL
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
P
IN
A
SSIGNMENT
V
DDO
nQ0
nQ1
nQ2
Q0
Q1
Q2
0
1
Q0
nQ0
Q1
nQ1
25
GND
CLK_SEL
HSTL_CLK
V
DD
nHSTL_CLK
PECL_CLK
nPECL_CLK
26
27
28
1
2
3
4
5
nQ8
24
23 22
21
20
19
18
17
16
Q3
nQ3
Q4
V
DDO
nQ4
Q5
nQ5
ICS852911I
15
14
13
6
Q8
7
nQ7
8
V
DDO
9
Q7
10
nQ6
12
11
Q6
28-Lead PLCC
11.6mm x 11.4mm x 4.1mm package body
V Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A January 21, 2016
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