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IDT70V3579S5BFI

Description
Dual-Port SRAM, 32KX36, 5ns, CMOS, PBGA208, FINE PITCH, BGA-208
Categorystorage    storage   
File Size185KB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70V3579S5BFI Overview

Dual-Port SRAM, 32KX36, 5ns, CMOS, PBGA208, FINE PITCH, BGA-208

IDT70V3579S5BFI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeBGA
package instructionTFBGA, BGA208,17X17,32
Contacts208
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
Maximum access time5 ns
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
JESD-30 codeS-PBGA-B208
JESD-609 codee0
length15 mm
memory density1179648 bit
Memory IC TypeDUAL-PORT SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals208
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA208,17X17,32
Package shapeSQUARE
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Minimum standby current3.15 V
Maximum slew rate0.415 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
width15 mm
Base Number Matches1
HIGH-SPEED 3.3V 32K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
x
x
IDT70V3579S
x
x
x
x
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5/6ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
x
x
x
x
x
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP) and
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid
Array
Functional Block Diagram
BE
3L
BE
3R
BE
2L
BE
1L
BE
0L
BE
2R
BE
1R
BE
0R
R/W
L
B
W
0
L
B
W
1
L
B B
WW
2 3
L L
B
W
3
R
BB
WW
2 1
RR
B
W
0
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
OE
R
32K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
14L
A
0L
CNTRST
L
ADS
L
CNTEN
L
CLK
R
,
Counter/
Address
Reg.
A
14R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
CNTRST
R
ADS
R
CNTEN
R
4830 tbl 01
JULY 2001
1
©2001 Integrated Device Technology, Inc.
DSC 4830/13
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