FQ00 · FQ01 · FQ02 · FQ03 · FQ04 · FQ05
FlexQ
TM
Async
5 Volt Asynchronous x9 First-In/First-Out Queue
Memory Configuration
8,192 x 9
4,096 x 9
2,048 x 9
Device
FQ05
FQ04
FQ03
Memory Configuration
1,024 x 9
512 x 9
256 x 9
Device
FQ02
FQ01
FQ00
Key Features:
•
•
•
•
•
•
•
•
Industry leading First-In/First-Out Queues (up to 50MHz)
Independent Write and Read cycle time
Asynchronous and simultaneous Read and Write
5V power supply
Fully expandable in both word depth and width
Retransmit capability
Full, Empty, and Half Full flag indicators
Available packages: 28 - pin Plastic Dual In-line Package (PDIP), 28 - pin Plastic Thin Dual In-line Package
(PTDIP), 28 - pin Small Outline Integrated Circuit (SOIC), 32 – pin Thin Quad Flat Pack (TQFP), 32 - pin
Plastic Lead Chip Carrier (PLCC)
(0
°
C to 70
°
C) Commercial operating temperature available for access time of 12ns and above
(-40
°
C to 85
°
C) Industrial operating temperature available for access time of 25ns
Pin-to-pin compatible with IDT (7200, 7201, 7202, 7203, 7204, 7205) and Cypress (CY7C419, CY7C421,
CY7C425, CY7C429, CY7C433, CY7C460A)
•
•
•
Product Description:
HBA’s FlexQ™ Async FIFO offers industry leading 0.25um process technology and memory densities from 256 x 9 to 8,192 x
9. System designer has full flexibility of implementing deeper and wider queues using the depth and width expansion features.
Full and Empty indicators allow easy handshaking between transmitters and receivers.
Independent Write and Read controls provide rate-matching capability. System designer can re-read data from the starting
________
__________
position by using Retransmit (RET). Retransmit allows reset of the read pointer to its initial position. Half Full flag (HALF) is
available in the single device mode and width expansion mode, but not in depth expansion mode.
These FlexQ™ Async devices have low power consumption, hence minimizing system power requirements. In addition,
industry standard 28 - pin PDIP, 28 – pin PTDIP, 28 – pin SOIC, 32 – pin TQFP and 32 - pin PLCC are offered to save system
board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, medical systems, network switching, etc.
5FA09C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2003
Page 1 of 14
FQ00 · FQ01 · FQ02 · FQ03 · FQ04 · FQ05
FlexQ
TM
Async
WRITE (
W
)
DATA IN (D
8 - 0
)
FULL (
FULL
)
RESET ( RST )
FQ00
FQ01
FQ02
FQ03
FQ04
FQ05
READ (
R
)
DATA OUT (Q
8 - 0
)
EMPTY (
EMPTY
)
RETRANSMIT ( RET )
EXPANSION OUT / HALF (
XO/
HALF
)
EXPANSION IN ( XI )
FIRST LOAD (
FIRST
)
Figure 1. Single Device Configuration Signal Flow Diagram
Block Diagram of Single Asynchronous Queue
8,192 x 9 / 4,096 x 9 / 2,048 x 9 / 1,024 x 9 / 512 x 9 / 256 x 9
W
Write Control
Logic
RST
RET
Reset Logic
Write Pointer
D
8-0
Input Register
SRAM
Output Register
Output
Buffer
Q
8-0
Read Pointer
FIRST
XI
EMPTY
Expansion
Logic
XO
Read Control
Logic
Flag
Logic
FULL
HALF
R
Figure 2. Device Architecture
5FA09C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2003
Page 2 of 14
FQ00 · FQ01 · FQ02 · FQ03 · FQ04 · FQ05
FlexQ
TM
Async
Vcc
NC
D3
D8
D4
D5
Index
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V cc
D4
D5
D6
D7
FIRST /
RET
W
D8
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
15
16
17
18
19
20
D2
D1
D0
XI
FULL
Q0
Q1
NC
Q2
5
6
7
8
9
10
11
12
13
14
D6
D7
NC
FIRST /
RET
D3
D2
D1
D0
XI
FULL
Q0
Q1
Q2
Q3
Q8
RST
EM PTY
X O /
HALF
RST
EM PTY
X O /
HALF
Q7
Q6
Q7
Q6
Q5
Q4
R
Q4
GND
Q3
Q8
NC
Q5
R
GND
PL CC - 32 (Drw No: J-01A; O rder code: J)
Top View
Plastic DIP - 28 (Drw No: P-01A; O rder code: P)
Plastic Thin DIP - 28 (Drw N o: T P-01A; O rder code: TP)
SO IC - 28 (Drw No: SO -01A; O rder code: SO )
Vcc
T op View
D4
D5
26
D3
D2
D8
Index
32
31
30
29
28
27
25
24
23
22
21
20
19
18
17
9
D6
W
D1
D0
NC
NC
XI
FULL
Q0
Q1
1
2
3
4
5
6
7
8
D7
FIRST / RET
NC
NC
RST
EM PTY
X O /
HALF
Q7
10
11
12
13
14
15
16
GND
Q2
Q3
Q8
T Q FP - 32 (D rw No: PF-04A; O rder code: PF)
Top V iew
Figure 3. Device Pin-Out
Q4
Q5
Q6
R
5FA09C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2003
Page 3 of 14
FQ00 · FQ01 · FQ02 · FQ03 · FQ04 · FQ05
FlexQ
TM
Async
Pin #
J
Pin #
P, TP,
SO
22
Pin #
PF
Symbol
Name
Input/
Output
Description
Reset is required to initialize Write and Read pointers to
the first position of the queue by setting RST low.
FULL
will go high; EMPTY will go low.
____
25
20
RST
____
Reset
Input
2
3, 4, 5,
6, 7, 28,
29, 30,
31
18
10, 11,
13, 14,
15, 19,
20, 21,
22
1
2, 3, 4,
5, 6, 24,
25, 26,
27
15
9, 10,
11, 12,
13, 16,
17, 18,
19
29
1, 2, 24,
25, 26,
27, 30,
31, 32
13
7, 8, 9,
10, 11,
14, 15,
16, 17
W
Write
Input
Writes data into queue during low to high transitions of
W if queue is not full yet.
D
8 - 0
Data Inputs
Input
9 - bit wide input data bus.
___
R
Read
Input
___
Reads data from queue during high to low transitions of
R if queue is not empty.
Q
8 - 0
Data Output
Output
9 - bit wide output data bus.
___________
26
23
23
FIRST /
________
RET
First Load/
Retransmit
Input
FIRST / RET is used differently depending on mode. In
Depth Expansion Mode, the pin is grounded to indicate
first load. In Single Device Mode, the pin acts as
retransmit.
XI is used to indicate operations in different modes.
When the pin is grounded, it indicates an operation in the
Single Device Mode. When it is tied to Vcc, it indicates
an operation in Depth Expansion Mode.
Queue is full when
FULL
goes low. This prohibits
further writes into the queue. The assertion of
FULL
is
____
synchronous to the falling edge of W and the deassertion
___
is synchronous to the rising edge of R .
Queue is empty when EMPTY goes low. This prohibits
further reads from the queue. The assertion of EMPTY
___
is synchronous to the falling edge of R and the
____
deassertion is synchronous to the rising edge of W.
XO / HALF is used differently depending on mode. In
____
Depth Expansion Mode, XI is connected to the previous
______
device’s XO pin. When the previous device has reached
the last location of memory, this pin will send pulses to
the next device in the Daisy Chain. In Single Device
____
Mode, when XI is grounded, this pin indicates queue is
half-full.
5V power supply.
0V Ground.
No connection.
______
__________
____
___________
________
8
7
5
XI
____
Expansion In
Input
9
8
6
FULL
Full Flag
Output
24
21
19
EMPTY
Empty Flag
Output
23
20
18
XO /
__________
HALF
______
Expansion Out /
Half Full Flag
Output
32
16
1, 12,
17, 27
28
14
N/A
28
12
3, 4, 21,
22
Vcc
GND
NC
Power
Ground
No Connection
N/A
N/A
N/A
Table 1. Pin Descriptions
5FA09C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2003
Page 4 of 14
FQ00 · FQ01 · FQ02 · FQ03 · FQ04 · FQ05
FlexQ
TM
Async
Symbol
Rating
Terminal Voltage with
respect to GND
Storage Temperature
DC Output Current
Com’l & Ind’l
-0.5 to + 7
-55 to +125
-50 to +50
Unit
V
°
V
TERM
T
STG
I
OUT
NOTES:
Absolute Max Ratings are for reference only. Permanent damage to the device may
occur if extended period of operation is outside this range. Standard operation should
fall within the Recommended Operating Conditions
.
C
mA
Table 2. Absolute Maximum Ratings
FQ05, FQ04, FQ03, FQ02, FQ01, FQ00
Commercial t
A
= 12ns, 25ns,
35ns, 50ns
Min.
Typ.
Max.
4.5
0
2.0
-
0
5.0
0
-
-
-
5.5
0
-
0.8
70
Industrial t
A
= 25ns
Min.
4.5
0
2.0
-
-40
Symbol
Parameter
Recommended Operating Conditions
Typ.
5.0
0
-
-
-
Max.
5.5
0
-
0.8
85
Unit
V
V
V
V
°
V
CC
GND
Supply Voltage Com’l/Ind’l
Supply Voltage
Input High Voltage
Com’l/Ind’l
Input Low Voltage
Com’l/Ind’l
Operating Temperature
Input Leakage Current (any
input)
Output Leakage Current
Output Logic “1” Voltage,
I
OH
=-2mA
Output Logic “0” Voltage,
I
OL
= 8mA
Active Power Supply
Current
Standby Current
V
IH
V
IL
T
A
I
LI
(1)
I
LO
V
OH
V
OL
Power Consumption
C
DC Electrical Characteristics
-10
-10
2.4
-
-
-
-
-
10
10
-
0.4
-10
-10
2.4
-
-
-
-
-
10
10
-
0.4
µ
A
µ
A
V
V
I
CC
1
(2,3,4)
I
CC
2
(2,5)
-
-
-
-
80
5
-
-
-
-
80
5
mA
mA
Capacitance at 1.0MHz Ambient Temperature (25°C)
Symbol
Parameter
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
8
Unit
pF
pF
C
IN(6)
C
OUT(6)
NOTES:
1.
2.
3.
4.
5.
6.
Input Capacitance
Output Capacitance
Measurement with 0.4<=V
IN
<=Vcc
Tested with outputs open (I
OUT
=0)
Tested at f=20MHz
Typical Icc1=15+2*fs+0.02*C
L
*fc (in mA) with Vcc=5V, t
A
=25
°
C, fs=WCLK frequency=RCLK frequency (in MHz, using TTL levels), data switching
at fs/2, C
L
=Capacitive load (in PF)
___ ____ _______ ___________ ________
All inputs = Vcc-0.2V or GND+0.2V and (R =W =RST=FIRST/RET=V
IH
)
Design simulated, not tested.
Table 3. DC Specifications
5FA09C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
AUGUST 2003
Page 5 of 14
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