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MC74AC109

Description
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
File Size85KB,6 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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MC74AC109 Overview

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

MC74AC109
MC74ACT109
Dual JK Positive
Edge Triggered Flip Flop
The MC74AC109/74ACT109 consists of two high-speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise and fall
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Outputs Source/Sink 24 mA
• ′ACT109
Has TTL Compatible Inputs
VCC
16
CD2
15
CD
DUAL JK POSITIVE
EDGE-TRIGGERED
FLIP-FLOP
N SUFFIX
CASE 648-08
PLASTIC
Q2
9
J2
14
J
K2
13
K
CP2
12
CP
SD2
11
SD
Q2
10
Q
Q
PIN NAMES
CD1
J1
K1
CP1
SD1
Q1
Q1
1
CD1
2
J1
3
K1
4
CP1
5
SD1
6
Q1
7
Q1
8
GND
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
TRUTH TABLE
Inputs
SD
L
H
L
H
H
H
H
H
CD
H
L
L
H
H
H
H
H
CP
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Outputs
Q
H
L
H
L
Q
Q
SD
J
CP
K
Q
CD
L
L
H
H
H
Toggle
Q0
Q0-
H
L
Q0
Q0-
Q
SD
J
CP
Q
CD
K
H = HIGH Voltage Level
L = LOW Voltage Level
= LOW-to-HIGH Clock Transition
X = Immaterial
Q0(Q0) = Previous Q0(Q0) before
LOW-to-HIGH Transition of Clock
FACT DATA
5-1

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