NXP Semiconductors
Advance Information
Document Number: MC33GD3000
Rev. 7.0, 4/2019
Three phase field effect transistor
pre-driver
The 33GD3000 is a field effect transistor (FET) pre-driver designed for three
phase motor control and similar applications. It meets the stringent
requirements of automotive applications and is fully AEC-Q100 grade 1
qualified.
The IC contains three high-side FET pre-drivers and three low-side FET pre-
drivers. Three external bootstrap capacitors provide gate charge to the high-
side FETs.
The IC interfaces to a MCU via six direct input control signals, an SPI port for
device setup and asynchronous reset, enable and interrupt signals. Both 5.0 V
and 3.0 V logic level inputs are accepted and 5.0 V logic level outputs are
provided. The integrated circuit (IC) uses SMARTMOS technology.
Features
•
•
•
•
•
•
•
•
Fully specified from 8.0 V to 40 V covers 12 V and 24 V automotive systems
Extended operating range from 6.0 V to 60 V covers 12 V and 48 V systems
Gate drive capability of 1.0 A to 2.5 A
Protection against reverse charge injection from CGD and CGS of external
FETs
Includes a charge pump to support full FET drive at low battery voltages
Dead time is programmable via the SPI port
Simultaneous output capability enabled via safe SPI command
AEC-Q100 grade 1 qualified
33GD3000
THREE PHASE PRE-DRIVER
EP SUFFIX (Pb-FREE)
98ASA00654D
56-PIN QFN
Applications
Automotive systems
• Electro-hydraulic and electric power steering
• Braking pump
• Engine and transmission control
• Belt Starter Generator
• Turbo pump
• Actuator control
• Motor control
V
SYS
33GD3000
VPUMP
PUMP
VPWR
VLS
VDD
VSS
3
3
3
VSUP
PA_HS_G
PB_HS_G
PC_HS_G
PA_HS_S
PB_HS_S
PC_HS_S
MCU
OR
DSP
PX_HS
PX_LS
PHASEX
CS
SI
SCLK
SO
RST
INT
EN1
EN2
GND
PA_LS_G
PB_LS_G
PC_LS_G
PX_LS_S
AMP_P
AMP_N
AMP_OUT
R
SEN
Figure 1. 33GD3000 simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP B.V. 2019.
1
Orderable parts
Table 1. Orderable part variations
Part number
MC33GD3000EP
(1)
Temperature (T
A
)
-40 °C to 125 °C
Package
56-pin QFN
Notes
1.
To order parts in tape and reel, add the R2 suffix to the part number.
33GD3000
2
Analog Integrated Circuit Device Data
NXP Semiconductors
2
Internal block diagram
PUMP
VPWR
VSUP
VPUMP
PGND
MAIN
CHARGE
PUMP
TRICKLE
CHARGE
PUMP
5.0 V
REG.
VDD
OSCILLATOR
UV
DETECT
3X
HOLD
-OFF
CIRCUIT
VLS
REG.
VLS
VDD
RST
INT
EN1
EN2
PX_HS
PX_LS
CS
SI
SCLK
SO
PHASEX
OC_OUT
GND(2)
+
-
OVERCURRENT
COMP.
3
3
3
T-LIM
VSUP
+
DESAT. 1.4 V
-
COMP
+
-
HIGH-
SIDE
DRIVER
PX_BOOT
PX_HS_G
CONTROL
LOGIC
PX_HS_S
+
-
PHASE
VSUP
COMP.
LOW-
SIDE
DRIVER
PX_LS_G
+
-
I-SENSE
AMP.
AMP_N
AMP_P
VLS_CAP
PX_LS_S
VSS OC_TH AMP_OUT
Figure 2. 33GD3000 simplified internal block diagram
33GD3000
Analog Integrated Circuit Device Data
NXP Semiconductors
3
3
3.1
Pin connections
Pinout diagram
PC_BOOT
PB_BOOT
PC_HS_G
PB_HS_G
PC_HS_S
PA_HS_G
PB_HS_S
PB_LS_G
PC_LS_G
44
PA_HS_S
56
55
54
53
52
51
50
49
48
47
46
45
PC_LS_S
43
42
NC
41
NC
40
VLS_CAP
39
GND
38
GND
37
VSS
36
OC_TH
35
OC_OUT
34
AMP_P
33
AMP_N
32
AMP_OUT
31
PC_HS_B
30
PC_LS
29
SO
28
PA_LS_G
PA_BOOT
1
NC
2
NC
3
VLS
4
NC
5
VPWR
6
NC
7
PHASEA
8
PGND
9
EN1
10
EN2
11
RST_B
12
NC
13
PUMP
14
15
16
17
18
19
20
21
22
23
24
25
26
27
EP
PA_HS_B
VPUMP
VSUP
PHASEB
PHASEC
PB_HS_B
PB_LS_S
PA_LS_S
Transparent
Top View
PA_LS
PB_LS
CS_B
Figure 3. 33GD3000 pin connections
A functional description of each pin can be found in the
Functional pin description
section beginning on
page 21.
Table 2. 33GD3000 pin definitions
Pin
1
2, 3, 5, 7, 13,
17, 41, 42
4
6
8
9
Pin name
PA_BOOT
NC
VLS
VPWR
PHASEA
PGND
Pin function
Analog input
No connect
Analog output
Power input
Digital output
Ground
VLS regulator
Voltage power
Phase A
Power ground
Formal name
Phase A bootstrap
Definition
Bootstrap capacitor for Phase A
No connection
VLS regulator output; power supply for the gate drives
Power supply input for gate drives
Totem pole output of Phase A comparator; this output is low when the
voltage on PA_HS_S (source of high-side FET) is less than 50% of V
SUP
Power ground for charge pump
33GD3000
4
SCLK
NC
VDD
INT
SI
Analog Integrated Circuit Device Data
NXP Semiconductors
Table 2. 33GD3000 pin definitions
Pin
10
11
12
14
15
16
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38, 39
40
43
44
Pin name
EN1
EN2
RST_B
PUMP
VPUMP
VSUP
PHASEB
PHASEC
PA_HS_B
PA_LS
VDD
PB_HS_B
PB_LS
INT
CS_B
SI
SCLK
SO
PC_LS
PC_HS_B
AMP_OUT
AMP_N
AMP_P
OC_OUT
OC_TH
VSS
GND
VLS_CAP
PC_LS_S
PC_LS_G
Pin function
Digital input
Digital input
Digital input
Power drive out
Power input
Analog input
Digital output
Digital output
Digital input
Digital input
Analog output
Digital input
Digital input
Digital output
Digital input
Digital input
Digital input
Digital output
Digital input
Digital input
Analog output
Analog input
Analog input
Digital output
Analog input
Ground
Ground
Analog output
Power input
Power output
Formal name
Enable 1
Enable 2
Reset
Pump
Voltage pump
Supply voltage
Phase B
Phase C
Phase A high-side
Phase A low-side
VDD regulator
Phase B high-side
Phase B low-side
Interrupt
Chip select
Serial in
Serial clock
Serial out
Phase C low-side
Phase C high-side
Amplifier output
Amplifier invert
Amplifier non-invert
Overcurrent out
Overcurrent threshold
Voltage source supply
Ground
VLS regulator output
capacitor
Phase C low-side
source
Phase C low-side gate
drive
Definition
Logic signal input must be high (ANDed with EN2) to enable any gate
drive output.
Logic signal input must be high (ANDed with EN1) to enable any gate
drive output
Reset input
Charge pump output
Charge pump supply
Supply voltage to the load. This pin is to be connected to the common
drains of the external high-side FETs
Totem pole output of Phase B comparator. This output is low when the
voltage on PB_HS_S (source of high-side FET) is less than 50% of V
SUP
Totem pole output of Phase C comparator. This output is low when the
voltage on PC_HS_S (source of high-side FET) is less than 50% of V
SUP
Active low input logic signal enables the high-side driver for Phase A
Active high input logic signal enables the low-side driver for Phase A
VDD regulator output capacitor connection
Active low input logic signal enables the high-side driver for Phase B
Active high input logic signal enables the low-side driver for Phase B
Interrupt pin output
Chip select input. It frames SPI commands and enables SPI port.
Input data for SPI port. Clocked on the falling edge of SCLK, MSB first
Clock for SPI port and typically is 3.0 MHz
Output data for SPI port. Tri-state until CS becomes low.
Active high input logic signal enables the low-side driver for Phase C
Active low input logic signal enables the high-side driver for Phase C
Output of the current-sensing amplifier
Inverting input of the current-sensing amplifier
Non-inverting input of the current-sensing amplifier
Totem pole digital output of the overcurrent comparator
Threshold of the overcurrent detector
Ground reference for logic interface and power supplies
Substrate and ESD reference, connect to VSS
VLS regulator connection for additional output capacitor, providing low
impedance supply source for low-side gate drive
Source connection for Phase C low-side FET
Gate drive output for Phase C low-side
33GD3000
Analog Integrated Circuit Device Data
NXP Semiconductors
5
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