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Datasheet> All Categories > logic> logic> MC54HCT245AJ
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MC54HCT245AJ

Description
Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs
Categorylogic    logic   
File Size112KB，8 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
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MC54HCT245AJ Overview

Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs

MC54HCT245AJ Parametric

Parameter NameAttribute value
MakerMotorola ( NXP )
Parts packaging codeDIP
package instructionDIP,
Contacts20
Reach Compliance Codeunknow
seriesHCT
JESD-30 codeR-CDIP-T20
JESD-609 codee0
length24.515 mm
Logic integrated circuit typeBUS TRANSCEIVER
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)33 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm

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Download Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting
Bus Transceiver with
LSTTL Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC54/74HCT245A is identical in pinout to the LS245. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
The MC54/74HCT245A is a 3–state noninverting transceiver that is
used for 2–way asynchronous communication between data buses. The
device has an active–low Output Enable pin, which is used to place the
I/O ports into high–impedance states. The Direction control determines
whether data flows from A to B or from B to A.
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•
Chip Complexity: 304 FETs or 76 Equivalent Gates
LOGIC DIAGRAM
A1
A2
A3
A
DATA
PORT
A4
A5
A6
A7
A8
DIRECTION
OUTPUT ENABLE
2
3
4
5
6
7
8
9
1
19
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
B
DATA
PORT
MC54/74HCT245A
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
20
1
20
1
ORDERING INFORMATION
Ceramic
MC54HCTXXXAJ
Plastic
MC74HCTXXXAN
SOIC
MC74HCTXXXADW
SSOP
MC74HCTXXXASD
TSSOP
MC74HCTXXXADT
PIN ASSIGNMENT
DIRECTION
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
OUTPUT ENABLE
B1
B2
B3
B4
B5
B6
B7
B8
PIN 20 = VCC
PIN 10 = GND
A5
A6
A7
A8
GND
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Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î Î
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ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î
Î Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Design Criteria
Value
76
Units
ea
ns
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
1.0
5.0
µW
pJ
0.005
* Equivalent to a two–input NAND gate.
2/97
FUNCTION TABLE
Control Inputs
Output
Enable
L
L
H
X = Don’t Care
Direction
L
H
X
Operation
O
i
Data Transmitted from Bus B to Bus A
Data Transmitted from Bus A to Bus B
Buses Isolated (High–Impedance State)
©
Motorola, Inc. 1997
3–1
REV 7

MC54HCT245AJ Related Products

MC54HCT245AJ MC74HCT245ASD MC74HCT245ADW MC74HCT245ADT MC74HCT245AN
Description Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs Octal 3-State Noninverting Bus Transceiver with LSTTL Compatible Inputs
Maker Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP )
package instruction DIP, SSOP, SOP, PLASTIC, TSSOP-20 DIP,
Reach Compliance Code unknow unknown unknow unknow unknow
series HCT HCT HCT HCT HCT
JESD-30 code R-CDIP-T20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDIP-T20
JESD-609 code e0 e0 e0 e0 e0
length 24.515 mm 7.2 mm 12.8 mm 6.5 mm 26.415 mm
Logic integrated circuit type BUS TRANSCEIVER BUS DRIVER BUS TRANSCEIVER BUS TRANSCEIVER BUS TRANSCEIVER
Number of digits 8 8 8 8 8
Number of functions 1 1 1 1 1
Number of ports 2 2 2 2 2
Number of terminals 20 20 20 20 20
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C -55 °C -55 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE TRUE TRUE
Package body material CERAMIC, METAL-SEALED COFIRED PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP SSOP SOP TSSOP DIP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH IN-LINE
propagation delay (tpd) 33 ns 33 ns 33 ns 33 ns 33 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 5.08 mm 2 mm 2.65 mm 1.2 mm 4.57 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V
surface mount NO YES YES YES NO
technology CMOS CMOS CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY MILITARY MILITARY
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE GULL WING GULL WING GULL WING THROUGH-HOLE
Terminal pitch 2.54 mm 0.65 mm 1.27 mm 0.65 mm 2.54 mm
Terminal location DUAL DUAL DUAL DUAL DUAL
width 7.62 mm 5.3 mm 7.5 mm 4.4 mm 7.62 mm
Parts packaging code DIP SSOP SOIC - DIP
Contacts 20 20 20 - 20

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