MC54/74F85
4-BIT MAGNITUDE COMPARATOR
The MC54/74F85 is a 4-Bit Magnitude Comparator which compares two
4-Bit words (A0-A3, B0-B3), A3, B3 being the most significant inputs. Operation
is not restricted to binary codes; the device will work with any monotonic code.
Three Outputs are provided: “A greater than B” (0A > B), “A less than B” (0A
< B), “A equal to B” (0A = B). Three Expander Inputs, IA > B, IA < B, IA = B, allow
cascading without external gates. For proper compare operation, the Expan-
der Inputs to the least significant position must be connected as follows: IA <
B = IA > B = L, IA = B = H. For serial (ripple) expansion the 0A > B, 0A < B Outputs
are connected respectively to the IA > B and IA = B inputs of the next most sig-
nificant comparator, as shown in Figure 1. Refer to applications section of
data sheet for high speed method of comparing large words.
4-BIT MAGNITUDE COMPARATOR
FAST™ SCHOTTKY TTL
•
High Impedance NPN Base Inputs for Reduced Loading (20
µA
in
HIGH and LOW States)
•
Magnitude Comparison of any Binary Words
•
Serial or Parallel Expansion Without Extra Gating
•
ESD > 4000 Volts
CONNECTION DIAGRAM
VCC
16
A3
15
B2
14
A2
13
A1
12
B1
11
A0
10
B0
9
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
B3
2
IA<B
3
IA=B
4
IA>B
5
A>B
6
A=B
7
A<B
8
GND
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
MC74FXXJ
MC74FXXN
MC74FXXD
Ceramic
Plastic
SOIC
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
Supply Voltage
Operating Ambient Temperature Range
Parameter
54, 74
54
74
IOH
IOL
Output Current
High
Output Current
Low
54, 74
54, 74
Min
4.5
–55
0
Typ
5.0
25
25
Max
5.5
125
70
–1.0
20
mA
mA
Unit
V
°C
FAST AND LS TTL DATA
4-36
MC54/74F85
FUNCTION TABLE
Comparing Inputs
A3, B3
A3 > B3
A3 < B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A2, B2
X
X
A2 > B2
A2 < B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A1, B1
X
X
X
X
A1 > B1
A1 < B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A0, B0
X
X
X
X
X
X
A0 > B0
A0 < B0
A0 = B0
A0 = B0
A0 = B0
A0 = B0
A0 = B0
A0 = B0
IA > B
X
X
X
X
X
X
X
X
H
L
L
X
H
L
Expansion Inputs
IA < B
X
X
X
X
X
X
X
X
L
H
L
X
H
L
IA = B
X
X
X
X
X
X
X
X
L
L
H
H
L
L
A>B
H
L
H
L
H
L
H
L
H
L
L
L
L
H
Outputs
A<B
L
H
L
H
L
H
L
H
L
H
L
L
L
H
A=B
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54, 74
74
VOL
IIH
Output LOW Voltage
Input HIGH Current
2.5
2.7
0.5
20
0.1
IIL
IOS
Input LOW Current
Output Short Circuit Current (Note 2)
Total Supply Current
ICC
HIGH VIN = HIGH
LOW An = Bn = IA-B = GND: IA>B = IA<B = 4.5 V
50
54
mA
VCC = MAX
–60
–20
–150
V
µA
mA
µA
mA
Parameter
Min
2.0
0.8
–1.2
Typ
Max
Unit
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage
Guaranteed Input LOW Voltage
VCC = MIN, IIN = –18 mA
IOH = –1.0 mA
VCC = 4.50 V
VCC = 4.75 V
IOL = 20 mA, VCC = MIN
VCC = MAX, VIN = 2.7 V
VCC = 0 V, VIN = 7.0 V
VCC = MAX, VIN = 0.5 V
VCC = MAX, VOUT = 0 V
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
4-37
MC54/74F85
(MSB) B23
A23
B22
A22
B21
A21
B20
A20
B19
A19
L
B3
A3
B2
A2
B1
A1
B0
A0
IA < B
IA = B
IA > B
A<B
A=B
A>B
NC
B18
A18
B17
A17
B16
A16
B15
A15
B14
L
A14
B3
A3
B2
A2
B1
A1
B0
A0
IA < B
IA = B
IA > B
A<B
A=B
A>B
NC
The parallel expansion scheme shown in Figure 1 demon-
strates the most efficient general use of these comparators.
In the parallel expansion scheme, the expansion inputs can
be used as a fifth input bit position except on the least signifi-
cant device which must be connected as in the Serial
Scheme. The expansion inputs are used by labelling IA>B
as an “A” input, IA<B as a “B” input and setting IA=B low. The
‘F85 can be used as a 5-bit comparator only when the out-
puts are used to drive the (A0-A3) and (B0-B3) inputs of
another ‘F85 device. The parallel technique can be ex-
panded to any number of bits as shown in Table 1.
B13
A13
B12
A12
B11
A11
B10
A10
B9
L
A9
B3
A3
B2
A2
B1
A1
B0
A0
IA < B
IA = B
IA > B
A<B
A=B
A>B
NC
B3
A3
B2
A2
B1
A1
B0
A0
A<B
A=B
A>B
A<B
A=B
A>B
OUTPUTS
B8
A8
B7
A7
B6
A6
B5
A5
B4
L
A4
B3
A3
B2
A2
B1
A1
B0
A0
IA < B
IA = B
IA > B
A<B
A=B
A>B
NC
Table 1
Word
Length
1–4 Bits
Number of
Packages
1
2–6
8–31
Typical Speeds
74F
12 ns
22 ns
34 ns
B3
A3
B2
A2
B1
A1
(LSB) B0
A0
L
H
L
B3
A3
B2
A2
B1
A1
B0
A0
IA < B
IA = B
IA > B
A<B
A=B
A>B
5–25 Bits
25–120 Bits
Figure 1. Comparison of Two 24-Bit Words
FAST AND LS TTL DATA
4-38
MC54/74F85
AC ELECTRICAL CHARACTERISTICS
54/74F
TA = +25°C
VCC = +5.0 V
CL = 50 pF
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
A or B Input to
A < B, A > B Output
A or B Input to
A = B Output
IA<B and IA=B Input
to A>B Output
IA=B Input to
A = B Output
IA>B and IA=B Input
to A<B Output
Min
6.0
6.0
5.5
7.0
3.0
3.0
2.5
3.5
3.0
3.0
Max
11
14
11.5
14
7.5
9.0
7.0
10
8.0
9.0
54F
TA = –55°C to +125°C
VCC = 5.0 V
±
10%
CL = 50 pF
Min
5.5
5.5
5.0
6.5
2.5
2.5
2.0
2.5
3.0
2.0
Max
14
16.5
15
15.5
10
11
10
13
10.5
10.5
74F
TA = 0°C to + 70°C
VCC = 5.0 V
±
10%
CL = 50 pF
Min
5.5
5.5
5.0
6.5
2.5
2.5
2.0
2.5
3.0
2.0
Max
13
ns
15.5
14
ns
14.5
9.0
ns
10
9.0
ns
12
9.5
ns
9.5
Unit
The expansion inputs IA>B, IA=B, and IA<B are the least sig-
nificant bit positions. When used for series expansion, the
A>B, A=B, and A<B outputs of the least significant word are
connected to the corresponding IA>B, IA=B, and IA<B inputs of
the next higher stage. Stages can be added in this manner
to any length, but a propagation delay penalty of about 15 ns
is added with each additional stage. For proper operation the
expansion inputs of the least significant word should be tied
as follows: IA>B = LOW, IA=B = HIGH, and IA<B = LOW.
A3 (15)
B3
(1)
(5)
A2 (13)
B2 (14)
(2)
IA < B
IA = B (3)
IA > B
(4)
A1 (12)
B1 (11)
(7)
A>B
(6)
A=B
A<B
A0 (10)
B0
(9)
NOTE:
This diagram is provided only for the understanding of logic operations and should not be used
to estimate propagation delays.
Figure 2. Logic Diagram
FAST AND LS TTL DATA
4-39
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