B-16
01/99
2N4856A, 2N4857A, 2N4858A, 2N4859A, 2N4860A, 2N4861A
N-Channel Silicon Junction Field-Effect Transistor
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Absolute maximum ratings at T
A
= 25¡C
2N4856A, 2N4857A, 2N4858A
Reverse Gate Source Voltage
– 40 V
Reverse Gate Drain Voltage
– 40 V
Continuous Device Dissipation
1.8 W
Continuous Forward Gate Current
50 mA
Power Derating
10 mA/°C
2N4859A, 2N4860A, 2N4861A
– 30 V
– 30 V
1.8 W
50 mA
10 mA/°C
At 25°C free air temperature:
Static Electrical Characteristics
Gate Source Breakdown Voltage
2N4856A, 2N4857A, 2N4858A
Gate Source Breakdown Voltage
2N4859A, 2N4860A, 2N4861A
Gate Reverse Current
2N4856A, 2N4857A, 2N4858A
Gate Reverse Current
2N4859A, 2N4860A, 2N4861A
Gate Source Cutoff Voltage
Drain Saturation Current (Pulsed)
Drain Cutoff Current
Drain Source ON Voltage
Dynamic Electrical Characteristics
Common Source ON Resistance
Common Source Input Capacitance
Common Source Reverse
Transfer Capacitance
Switching Characteristics
Turn ON Delay Time
t
d(on)
r
ds(on)
C
iss
C
rss
V
(BR)GSS
V
(BR)GSS
I
GSS
I
GSS
V
GS(OFF)
I
DSS
I
D(OFF)
V
DS(ON)
2N4856A
2N4859A
Min
Max
– 40
– 30
– 250
– 500
– 250
– 500
–4
50
250
500
0.75
(20)
– 10
2N4857A
2N4860A
Min
Max
– 40
– 30
– 250
– 500
– 250
– 500
–2
20
–6
100
250
500
0.5
(10)
2N4858A
2N4861A
Min
Max
– 40
– 30
– 250
– 500
– 250
– 500
– 0.8
8
–4
80
250
500
0.5
(5)
Unit
V
V
pA
nA
pA
nA
V
mA
pA
nA
V
(mA)
Process NJ132
Test Conditions
I
G
= – 1 µA, V
DS
= ØV
I
G
= – 1 µA, V
DS
= ØV
V
GS
= – 20V, V
DS
= ØV
V
GS
= – 20V, V
DS
= ØV
V
GS
= – 15V, V
DS
= ØV
V
GS
= – 15V, V
DS
= ØV
V
DS
= 15V, I
D
= 0.5 nA
V
DS
= 15V, V
GS
= ØV
V
DS
= 15V, V
GS
= – 10V
V
DS
= 15V, V
GS
= – 10V
V
GS
= ØV, I
D
= ( )
T
A
= 150°C
T
A
= 150°C
T
A
= 150°C
25
10
4
40
10
3.5
60
10
3.5
Ω
pF
pF
V
GS
= ØV, I
D
= Ø A
V
DS
= ØV, V
GS
= – 10V
V
DS
= ØV, V
GS
= – 10V
f = 1 kHz
f = 1 MHz
f = 1 MHz
5
(20)
[–10]
3
(20)
[–10]
25
(20)
[–10]
6
(10)
[– 6]
4
(10)
[– 6]
40
(10)
[– 6]
8
(5)
[– 4]
8
(5)
[– 4]
80
(5)
[– 4]
ns
(mA)
[V]
ns
(mA)
[V]
ns
(mA)
[V]
V
DD
= 10V, V
GS
= ØV
I
D(ON)
= ( )
V
GS(OFF)
= [ ]
Rise Time
t
r
Turn OFF Delay Time
t
d(off)
(2N4856A, 2N4859A)
R
L
= 464Ω
(2N4857A, 2N4860A)
R
L
= 953Ω
(2N4858A, 2N486A1)
R
L
= 1910Ω
TOÐ18 Package
See Section G for Outline Dimensions
Surface Mount
SMP4856A, SMP4857A, SMP4858A,
SMP4859A, SMP4860A, SMP4861A
Pin Configuration
1 Source, 2 Drain, 3 Gate & Case
1000 N. Shiloh Road, Garland, TX 75042
(972) 487-1287
FAX
(972) 276-3375
www.interfet.com
Embedded System
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