MT42L192M64D3EU-3AT:A datasheet, PDF

Datasheet> All Categories > storage> storage> MT42L192M64D3EU-3AT:A

MT42L192M64D3EU-3AT:A: DescriptionDDR DRAM, 192MX64, CMOS, PBGA253, 11 X 11 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, GREEN, FBGA-253; Categorystorage storage; File Size2MB，172 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

Download Datasheet Parametric View All

MT42L192M64D3EU-3AT:A Overview

DDR DRAM, 192MX64, CMOS, PBGA253, 11 X 11 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, GREEN, FBGA-253

MT42L192M64D3EU-3AT:A Parametric

Parameter Name	Attribute value
Maker	Micron Technology
package instruction	VFBGA,
Reach Compliance Code	compliant
access mode	MULTI BANK PAGE BURST
Other features	SELF REFRESH; IT ALSO REQUIRES 1.2V NOM
JESD-30 code	S-PBGA-B253
length	11 mm
memory density	12884901888 bit
Memory IC Type	DDR DRAM
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	253
word count	201326592 words
character code	192000000
Operating mode	SYNCHRONOUS
organize	192MX64
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Maximum seat height	0.9 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
width	11 mm
Base Number Matches	1

Preview

Download Datasheet

View All

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Mobile LPDDR2 SDRAM

MT42L256M16D1, MT42L128M32D1, MT42L256M32D2,

MT42L128M64D2, MT42L512M32D4, MT42L192M64D3,

MT42L256M64D4, MT42L384M32D3

Features

• Ultra low-voltage core and I/O power supplies

– V

DD2

= 1.14–1.30V

– V

DDCA

DDQ

= 1.14–1.30V

– V

DD1

= 1.70–1.95V

• Clock frequency range

– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)

• Four-bit prefetch DDR architecture

• Eight internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on every CK edge

• Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

• Programmable READ and WRITE latencies (RL/WL)

• Programmable burst lengths: 4, 8, or 16

• Per-bank refresh for concurrent operation

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock stop capability

• RoHS-compliant, “green” packaging

Table 1: Key Timing Parameters

Speed Clock Rate Data Rate

Grade

(MHz)

(Mb/s/pin)

-18

-25

-3

533

400

333

1066

800

667

RCD/

Options

Marking

Typical

• V

DD2

: 1.2V

• Configuration

– 32 Meg x 16 x 8 banks x 1 die

256M16

– 16 Meg x 32 x 8 banks x 1 die

128M32

– 16 Meg x 32 x 8 banks x 2 die

256M32

– 1 (16 Meg x 32 x 8 banks) + 2 (32

384M32

Meg x 16 x 8 banks)

– 32 Meg x 16 x 8 banks x 4 die

512M32

– 16 Meg x 32 x 8 banks x 2 die

128M64

– 16 Meg x 32 x 8 banks x 3 die

192M64

– 16 Meg x 32 x 8 banks x 4 die

256M64

• Device type

– LPDDR2-S4, 1 die in package

– LPDDR2-S4, 2 die in package

– LPDDR2-S4, 3 die in package

– LPDDR2-S4, 4 die in package

• FBGA “green” package

– 134-ball FBGA (10mm x

GU, GV

11.5mm)

– 168-ball FBGA (12mm x 12mm)

LF, LG

– 216-ball FBGA (12mm x 12mm) LH, LK, LL, LM,

– 220-ball FBGA (14mm x 14mm)

LD, MP

– 240-ball FBGA (14mm x 14mm)

– 253-ball FBGA (11mm x 11mm)

EU, EV

• Timing – cycle time

– 1.875ns @ RL = 8

-18

– 2.5ns @ RL = 6

-25

– 3.0ns @ RL = 5

-3

• Operating temperature range

– From –30°C to +85°C

– From –40°C to +105°C

• Revision

Note:

1. For Fast

RCD/

RP, contact factory.

PDF: 09005aef84427aab

4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Features

Contents

General Description ....................................................................................................................................... 12

General Notes ............................................................................................................................................ 12

Specifications ........................................................................................................................................... 13

Package Block Diagrams ................................................................................................................................. 18

Package Dimensions ....................................................................................................................................... 24

Ball Assignments and Descriptions ................................................................................................................. 37

Functional Description ................................................................................................................................... 46

Power-Up ....................................................................................................................................................... 47

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 49

Power-Off ....................................................................................................................................................... 49

Uncontrolled Power-Off .............................................................................................................................. 50

Mode Register Definition ................................................................................................................................ 50

Mode Register Assignments and Definitions ................................................................................................ 50

ACTIVATE Command ..................................................................................................................................... 61

8-Bank Device Operation ............................................................................................................................ 61

Read and Write Access Modes ......................................................................................................................... 62

Burst READ Command ................................................................................................................................... 62

READs Interrupted by a READ ..................................................................................................................... 69

Burst WRITE Command .................................................................................................................................. 69

WRITEs Interrupted by a WRITE ................................................................................................................. 72

BURST TERMINATE Command ...................................................................................................................... 72

Write Data Mask ............................................................................................................................................. 74

PRECHARGE Command ................................................................................................................................. 75

READ Burst Followed by PRECHARGE ......................................................................................................... 76

WRITE Burst Followed by PRECHARGE ....................................................................................................... 77

Auto Precharge ........................................................................................................................................... 78

READ Burst with Auto Precharge ................................................................................................................. 78

WRITE Burst with Auto Precharge ............................................................................................................... 79

REFRESH Command ...................................................................................................................................... 81

REFRESH Requirements ............................................................................................................................. 87

SELF REFRESH Operation ............................................................................................................................... 89

Partial-Array Self Refresh – Bank Masking .................................................................................................... 90

Partial-Array Self Refresh – Segment Masking .............................................................................................. 91

MODE REGISTER READ ................................................................................................................................. 92

Temperature Sensor ................................................................................................................................... 94

DQ Calibration ........................................................................................................................................... 96

MODE REGISTER WRITE Command ............................................................................................................... 98

MRW RESET Command .............................................................................................................................. 98

MRW ZQ Calibration Commands ................................................................................................................ 99

ZQ External Resistor Value, Tolerance, and Capacitive Loading .................................................................... 101

Power-Down ................................................................................................................................................. 101

Deep Power-Down ........................................................................................................................................ 108

Input Clock Frequency Changes and Stop Events ............................................................................................ 109

Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 109

Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 110

NO OPERATION Command ........................................................................................................................... 110

Simplified Bus Interface State Diagram ....................................................................................................... 110

Truth Tables .................................................................................................................................................. 112

Electrical Specifications ................................................................................................................................. 120

Absolute Maximum Ratings ....................................................................................................................... 120

PDF: 09005aef84427aab

4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Recommended Resources

RF sniffer circuit

CA6140 lathe power-saving control circuit_2

input attenuator

Field effect transistor logic probe circuit

Quartz crystal and frequency dividing circuit

Light controlled switch using photoresistor

Why is the serial port sending data incorrect?: When only one data is sent, the data is correct, but when the data is sent continuously in the query mode, the data is wrong. Moreover, when judging whether the data end code is received, the query mo...; wuaiabab MCU

Getting a task done in another clock domain: If the clkA domain has a task that needs to be completed in the clkB domain, you can use the following design. [img]http://www.fpga4fun.com/images/CrossClockDomain.task.gif[/img] Here's one way to do ...; eeleader FPGA/CPLD

The latest embedded design textbook published in 2008, share the first two: Just got a new book, published in 2008...; besk Embedded System

Understanding and judging transistor saturation and deep saturation states: [size=4]Summary of transistor saturation problems: [/size] [size=4] [/size] [size=4]1. In actual work, Ib*β=V/R is often used as a condition for judging critical saturation. The Ib value calculated ba...; Aguilera Analogue and Mixed Signal

Survey: What microcontrollers do people use?: I have NEC, PIC. It seems that few people use NEC. Let's see if there will be others besides me....; clwzqq Embedded System

EEWORLD University ---- PSoC Creator Feature Overview: File Manager: PSoC Creator Feature Overview: File Manager : https://training.eeworld.com.cn/course/2005This tutorial demonstrates how to use the PSoC Creator Document Manager....; chenyy Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components