PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844011I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
F
EATURES
•
One differential LVDS output
•
Crystal oscillator interface, 18pF parallel resonant crystal
(20.4MHz - 28.3MHz)
•
Output frequency range: 81.66MHz - 113.33MHz
•
VCO range: 490MHz - 680MHz
•
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.75ps (typical)
•
3.3V or 2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS844011I is a Fibre Channel Clock
Generator and a member of the HiPerClocks
TM
HiPerClockS™
family of high performance devices from ICS.
The ICS844011I uses an 18pF parallel resonant
crystal over the range of 20.4MHz - 28.3MHz. For
Fibre Channel applications, a 26.5625MHz crystal is used.
The ICS844011I has excellent <1ps phase jitter per-
formance, over the 637kHz - 10MHz integration range. The
ICS844011I is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
IC
S
C
OMMON
C
ONFIGURATION
T
ABLE
- F
IBRE
C
HANNEL
Inputs
Crystal Frequency (MHz)
26.5625
25
M
24
24
N
6
6
Multiplication
Value M/N
4
4
Output Frequency
(MHz)
106.25
100
B
LOCK
D
IAGRAM
OE
Pullup
P
IN
A
SSIGNMENT
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
nQ
OE
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
N = ÷6
(fixed)
Q
nQ
ICS844011I
M = ÷24
(fixed)
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844011AGI
www.icst.com/products/hiperclocks.html
REV. A APRIL 18, 2006
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844011I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
Type
Description
Analog supply pin.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Output enable pin. When HIGH, Q/nQ output is active. When LOW, the Q/nQ
output is in a high impedance state. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
Core supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT,
XTAL_IN
OE
nQ, Q
V
DD
Power
Power
Input
Input
Output
Power
Pullup
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
844011AGI
www.icst.com/products/hiperclocks.html
2
REV. A APRIL 18, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844011I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
101.7°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
TBD
TBD
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
TBD
TBD
Maximum
2.625
2.625
Units
V
V
mA
mA
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
OE
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
844011AGI
www.icst.com/products/hiperclocks.html
3
REV. A APRIL 18, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844011I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
Test Conditions
Minimum
Typical
350
40
1.25
50
Maximum
Units
mV
mV
V
mV
T
ABLE
3D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
NOTE: Please refer to Parameter Measurement Information for output information.
T
ABLE
3E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
50
1.2
40
Maximum
Units
mV
mV
V
mV
NOTE: Please refer to Parameter Measurement Information for output information.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
20.4
Test Conditions
Minimum
Typical
Fundamental
28.3
50
7
1
MHz
Ω
pF
mW
Maximum
Units
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
106.25MHz @ Integration Range:
637kHz - 10MHz
100MHz @ Integration Range:
637kHz - 10MHz
20% to 80%
Test Conditions
Minimum
81.66
TBD
0.75
275
50
Typical
Maximum
113.33
Units
MHz
ps
ps
ps
%
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
106.25MHz @ Integration Range:
637kHz - 10MHz
100MHz @ Integration Range:
637kHz - 10MHz
20% to 80%
Test Conditions
Minimum
81.66
TBD
0.93
295
50
Typical
Maximum
113.33
Units
MHz
ps
ps
ps
%
REV. A APRIL 18, 2006
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
844011AGI
www.icst.com/products/hiperclocks.html
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844011I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- LVDS
C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Qx
3.3V±5%
POWER SUPPLY
+
Float GND
-
SCOPE
2.5V±5%
POWER SUPPLY
+
Float GND
-
Qx
SCOPE
LVDS
nQx
LVDS
nQx
LVDS 3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Phase Noise Plot
LVDS 2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQ
Noise Power
Q
t
PW
Phase Noise Mask
t
PERIOD
odc =
f
1
Offset Frequency
f
2
t
PW
t
PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS P
HASE
J
ITTER
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
V
DD
V
DD
out
80%
Clock
Outputs
80%
V
SW I N G
➤
DC Input
LVDS
out
➤
20%
t
R
t
F
20%
➤
V
OS
/Δ V
OS
O
UTPUT
R
ISE
/F
ALL
T
IME
V
DD
DD
out
O
FFSET
V
OLTAGE
S
ETUP
DC Input
LVDS
100
V
OD
/Δ V
OD
out
➤
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
844011AGI
www.icst.com/products/hiperclocks.html
5
➤
➤
REV. A APRIL 18, 2006
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