3D7005S-25 datasheet, PDF - EEWORLD Datasheet

3D7005S-25: DescriptionSilicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16; Categorylogic logic; File Size141KB，4 Pages; ManufacturerData Delay Devices; Environmental Compliance

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3D7005S-25 Overview

Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO16, 0.300 INCH, SOIC-16

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Data Delay Devices
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	compliant
Other features	INPUT TO 1ST TAP DELAY = 7.5+-0.5NS; BOTH LEADING & TRAILING EDGE ACCURACY; MAX RISE TIME CAPTURED
series	CMOS/TTL
Input frequency maximum value (fmax)	67 MHz
JESD-30 code	R-PDSO-G16
length	10.3 mm
Load capacitance (CL)	25 pF
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	27.5 ns
width	7.5 mm
Base Number Matches	1

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