2200DAG100JF2GB datasheet, PDF

2200DAG100JF2GB: DescriptionStrain Guage Sensor, Absolute, 0Psi Min, 100Psi Max, 0.15%, 1-11V, Cylindrical; CategoryThe sensor Sensor/transducer; File Size507KB，4 Pages; ManufacturerGems Sensors & Controls

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2200DAG100JF2GB Overview

Strain Guage Sensor, Absolute, 0Psi Min, 100Psi Max, 0.15%, 1-11V, Cylindrical

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Reach Compliance Code	unknown
Maximum accuracy(%)	0.15%
shell	STAINLESS STEEL
Nominal offset	1V
Maximum operating temperature	50 °C
Minimum operating temperature	-20 °C
Output range	1-11V
Output type	ANALOG VOLTAGE
Package Shape/Form	CYLINDRICAL
port type	9/16 MALE WITH SNUBBER
Maximum pressure range	100 Psi
Minimum pressure range
Pressure sensing mode	ABSOLUTE
Sensor/Transducer Type	PRESSURE SENSOR,STRAIN GUAGE
Maximum supply voltage	35 V
Minimum supply voltage	1.5 V
Termination type	METAL CABLE GLAND
Base Number Matches	1

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[Project source code] [Modelsim FAQ] Port 'xxxx' not found in the connected module: This article and design code were written by FPGA enthusiast Xiao Meige. Without the author's permission, this article is only allowed to be copied and reproduced on online forums, and the original au...; 小梅哥 FPGA/CPLD

An error in the CC3200 Out of Box Application example: When I first saw the temperature in the Out of Box example, I wondered if the temperature sensor was broken. Then I thought that the temperature unit might be Fahrenheit. For people who are used to us...; littleshrimp RF/Wirelessly

crc16 source code sharing: // Copyright 2007 Altera Corporation. All rights reserved. // Altera products are protected under numerous U.S. and foreign patents, // maskwork rights, copyrights and other intellectual property laws...; eeleader FPGA/CPLD

[FPGA Design Problem] Three signal edges in the sensitivity list in Verilog: Data is sent when the rising edge of clock clk and signal A is high at the same time, but signal A has a fixed cycle (maintaining the high of 8 clocks), but when the rising edge of clock clk happens, ...; eeleader FPGA/CPLD

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