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DG411, DG412, DG413
Data Sheet
November 27, 2006
FN3282.12
Monolithic Quad SPST, CMOS Analog
Switches
The DG411 series monolithic CMOS analog switches are
drop-in replacements for the popular DG211 and DG212
series devices. They include four independent single pole
throw (SPST) analog switches, and TTL and CMOS
compatible digital inputs.
These switches feature lower analog ON resistance (<35Ω)
and faster switch time (t
ON
<175ns) compared to the DG211
or DG212. Charge injection has been reduced, simplifying
sample and hold applications.
The improvements in the DG411 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 40V
P-P
signals. Power supplies may be
single-ended from +5V to 44V, or split from ±5V to ±20V.
The four switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with analog
signals is quite low over a ±15V analog input range. The
switches in the DG411 and DG412 are identical, differing only
in the polarity of the selection logic. Two of the switches in the
DG413 (#2 and #3) use the logic of the DG211 and DG411
(i.e., a logic “0” turns the switch ON) and the other two
switches use DG212 and DG412 positive logic. This permits
independent control of turn-on and turn-off times for SPDT
configurations, permitting “break-before-make” or “make-
before-break” operation with a minimum of external logic.
Features
• ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 35Ω
• Low Power Consumption (P
D
) . . . . . . . . . . . . . . . . . . <35mW
• Fast Switching Action
- t
ON
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175ns
- t
OFF
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145ns
• Low Charge Injection
• Upgrade from DG211, DG212
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1993, 1994, 1997, 1999, 2002, 2004-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
DG411, DG412, DG413
Ordering Information
PART NUMBER
DG411DJ
DG411DJZ (Note)
DG411DY*
DG411DYZ* (Note)
DG411DVZ* (Note)
DG412DJ
DG412DJZ (Note)
DG412DY*
DG412DYZ* (Note)
DG412DVZ* (Note)
DG413DJ
DG413DJZ (Note)
DG413DY*
DG413DYZ* (Note)
DG413DVZ* (Note)
PART MARKING
DG411DJ
DG411DJZ
DG411DY
DG411DYZ
DG411 DVZ
DG412DJ
DG412DJZ
DG412DY
DG412DYZ
DG412 DVZ
DG413DJ
DG413DJZ
DG413DY
DG413DYZ
DG413 DVZ
TEMP. RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
16 Ld PDIP
16 Ld PDIP** (Pb-free)
16 Ld SOIC
16 Ld SOIC (Pb-free)
16 Ld TSSOP (Pb-free)
16 Ld PDIP
16 Ld PDIP** (Pb-free)
16 Ld SOIC
16 Ld SOIC (Pb-free)
16 Ld TSSOP (Pb-free)
16 Ld PDIP
16 Ld PDIP** (Pb-free)
16 Ld SOIC
16 Ld SOIC (Pb-free)
16 Ld TSSOP (Pb-free)
PKG. DWG. #
E16.3
E16.3
M16.15
M16.15
M16.173
E16.3
E16.3
M16.15
M16.15
M16.173
E16.3
E16.3
M16.15
M16.15
M16.173
*Add “-T” suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
TRUTH TABLE
DG411
LOGIC
0
1
DG412
SWITCH
1, 4
Off
On
DG413
SWITCH
2, 3
On
Off
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
SYMBOL
IN
1
D
1
S
1
V-
GND
S
4
D
4
IN
4
IN
3
D
3
S
3
V
L
V+
S
2
D
2
IN
2
DESCRIPTION
Logic Control for Switch 1.
Drain (Output) Terminal for Switch 1.
Source (Input) Terminal for Switch 1.
Negative Power Supply Terminal.
Ground Terminal (Logic Common).
Source (Input) Terminal for Switch 4.
Drain (Output) Terminal for Switch 4.
Logic Control for Switch 4.
Logic Control for Switch 3.
Drain (Output) Terminal for Switch 3.
Source (Input) Terminal for Switch 3.
Logic Reference Voltage.
Positive Power Supply Terminal (Substrate).
Source (Input) Terminal for Switch 2.
Drain (Output) Terminal for Switch 2.
Logic Control for Switch 2.
SWITCH SWITCH
On
Off
Off
On
NOTE: Logic “0”
≤0.8V.
Logic “1”
≥2.4V.
Pinout
DG411, DG412, DG413
(16 LD PDIP, SOIC, TSSOP)
TOP VIEW
IN
1
1
D
1
2
S
1
3
V- 4
GND 5
S
4
6
D
4
7
IN
4
8
16
IN
2
15
D
2
14
S
2
13
V+
12
V
L
11
S
3
10
D
3
9 IN
3
10
11
12
13
14
15
16
2
FN3282.12
November 27, 2006
DG411, DG412, DG413
Functional Diagrams
Four SPST Switches per Package Switches Shown for Logic “1” Input
DG411
S
1
IN
1
D
1
S
2
IN
2
D
2
S
3
IN
3
D
3
S
4
IN
4
D
4
IN
4
D
4
IN
3
D
3
S
4
IN
4
D
4
IN
2
D
2
S
3
IN
3
D
3
S
4
IN
1
D
1
S
2
IN
2
D
2
S
3
DG412
S
1
IN
1
D
1
S
2
DG413
S
1
Schematic Diagram
V+
(1 Channel)
S
V-
V
L
V+
IN
X
D
GND
V-
3
FN3282.12
November 27, 2006
DG411, DG412, DG413
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
V
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) to (V+) +0.3V
Digital Inputs, V
S
, V
D
(Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA
Thermal Information
Thermal Resistance (Typical, Note 2)
θ
JA
(°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
150
Maximum Junction Temperature (Plastic Packages). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC and TSSOP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20V
(Max)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . .
≤20ns
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on S
X
, D
X
, or IN
X
exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, V
L
= 5V, V
IN
= 2.4V, 0.8V (Note 3),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 4) (NOTE 5) (NOTE 4)
MIN
TYP
MAX
UNITS
PARAMETER
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
ON
R
L
= 300Ω, C
L
= 35pF, V
S
=
±10V
(Figure 1)
25
85
-
-
-
-
-
-
-
-
-
-
-
110
-
100
-
25
5
68
-85
9
9
35
175
220
145
160
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
pC
dB
dB
pF
pF
pF
Turn-OFF Time, t
OFF
25
85
Break-Before-Make Time Delay
Charge Injection, Q (Figure 3)
OFF Isolation (Figure 5)
Crosstalk (Channel-to-Channel),
(Figure 4)
Source OFF Capacitance, C
S(OFF)
Drain OFF Capacitance, C
D(OFF)
Channel ON Capacitance,
C
D(ON)
+ C
S(ON)
DIGITAL INPUT CHARACTERISTICS
Input Current V
IN
Low, I
IL
Input Current V
IN
High, I
IH
DG413 Only, R
L
= 300Ω, C
L
= 35pF (Figure 2)
C
L
= 10nF, V
G
= 0V, R
G
= 0Ω
R
L
= 50Ω, C
L
= 5pF, f = 1MHz
25
25
25
25
f = 1MHz (Figure 6)
25
25
25
V
IN
Under Test = 0.8V, All Others = 2.4V
V
IN
Under Test = 2.4V, All Others = 0.8V
Full
Full
-0.5
-0.5
0.005
0.005
0.5
0.5
μA
μA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Drain-Source ON Resistance,
r
DS(ON)
I
S
=
I
S
=
±
±
10mA
10mA, V
D
=
±8.5V,
V+ = 13.5V, V- = -13.5V
Full
25
Full
-15
-
-
-
25
-
15
35
45
V
Ω
Ω
4
FN3282.12
November 27, 2006
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