•
CD4000B, CD4001B, CD4002B, CD4025B Types
COS/MOS NOR Gates
High-Voltage Types (20-Volt Rating)
Dual 3 Input
plus Inverter - CD4000B
Quad 2 Input - CD4001 B
Dual 4 Input - CD4002B
Triple 3 Input - CD4025B
Features:
• Propagation delay time
=
60 ns (typ.) at
CL
=
50 pF. VDD
=
10 V
• Buffered inputs and outputs
• Standardized symmetrical output characteristics
• 100% tested for maximum quiescent current at 20 V
• 5-V. 10-V. and 15-V parametric ratings
• Maximum input current of 1 IlA at 18 V
over full package-temperature range;
100 nA at 18 V and 25
0
C
• Noise margin (over full package temperature
range):
1 Vat VDD
=
5 V
2 V at VDD
=
10 V
2.5 V at VDD
=
15 V
• Meets all requirements of JEDEC Tentative
Standard No.13A. "Standard Specifications
for Description of "B" Series CMOS Devices"
Vss
RCA-CD4000B. CD4001 B. CD4002B. and
CD4025B NOR gates provide the system
designer with direct implementation of the
NOR function and supplement the existing
family of COS/MOS gates. All Inputs and
outputs are buffered.
The CD40008. C040018. C040028. and
CD40258 types are supplied in 14-lead
hermetic dual-in-line ceramic packages (0
and F suffixes), 14-lead dual-in-line plastiC
packages (E suffix), 14-lead ceramic flat
packages (K suffix), and in chip form (H
suffix).
CD4000B
FUNCTIONAL DIAGRAM
STATIC ELECTRICAL CHARACTERISTICS
CONDITIONS
Vo
(V)
VIN VDD
(V)
(V)
CHARACTER-
ISTIC
LIMITS AT INDICATED TEMPERATURES (OC)
Values at
-55. +25. +125
Apply to D.F.H Packages
Values at -40.
+25. +85
Apply to E Package
CD4001B
FUNCTIONAL DIAGRAM
UNITS
+25
-55
0.25
05
1
5
064
16
42
-2
-16
-42
-40
025
05
1
+85
7.5
15
30
150
042
11
28
-042
-13
-11
-28
005
005
005
495
995
1495
1
r;
3
4
35
7
11
+125
75
15
30
150
036
09
2,4
Min.
Typ.
001
001
0.01
002
1
26
68
-1
-32
-26
-68
0
0
0
5
10
15
Max.
0.25
0.5
1
5
)J.A
QUiescent DeVice
Current.
100 Max
-
-
0,5
0,10
0,15
0,20
0,5
0.10
0,15
0,5
0.5
0,10
0.15
0,5
0.10
0.15
0.5
0,10
0,15
5
10
15
20
5
10
15
5
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
18
-
-
-
-
051
13
34
-
-
04
05
15
4.6
2.5
95
135
5
061
15
4
-18
15
e
Output Low
(Smk) Current
IOL Mm
Output High
(Source)
Current,
IOH Mm
Output Voltage
Lew·Level.
VOL Max
Output Voltage
H Igh·Level.
VOH Mm
Input Low
Voltage,
VIL Max
Input High
Voltage.
VIH Min
Input Current
liN Max
e.
-
-0.64 -061
-036 -0.51
-1 15 -16
-09
-24
-13
-34
-
-
-
-
005
005
005
rnA
Vss
K.~
C040028
92e5'247'S
-4
FUNCTIONAL DIAGRAM
-
-
-
-
-
-
-
-
495
995
1495
-
-
-
15
3
4
V
,.
VDD
-
0.5.4.5
1.9
1.5.13.5
0.5
1
1.5
-
-
-
-
-
-
0.18
-
-
-
-
-
35
7
11
!
-
-
-
-
V
Vss
7
-
-
-
±O 1
)J.A
:to
1
!O1
1
±1
-
:!10- 5
CD4025B
FUNCTIONAL DIAGRAM
50
CD4000B, CD4001B, CD4002B, CD4025B Types
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should
be
selected so that
operation is always within the fol/owing ranges:
CHARACTERISTIC
Supply-Voltage Range (For T A
=
Full Package
Temperature Range)
MAXIMUM RATINGS.
Absolute-Maximum Values
LIMITS
MIN.
MAX.
UNITS
V
3
18
DC SUPPLY·VOL TAGE RANGE. (V DD )
-05 to +20 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE. ALL INPUTS
-05 to VDD +05 V
±10mA
DC INPUT CURRENT. ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (PD)
500mW
For T A
=
-40 to +60
0
C (PACKAGE TYPE E)
Derate Linearly at 12
mW/oC
to 200 mW
For T A
=
+60 to +85
0
C (PACKAGE TYPE E)
o
For
T A
=
-55
to
+100 C (PACKAGE TYPES D.
F)
500mW
Derate Linearly at 12
mW/oC
to 200 mW
For TA
=
+100 to +125 PC (PACKAGE TYPES D. F) ,
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA" FULL PACKAGE TEMPERATURE RANGE (All Package Types)
OPERATlNG·TEMPERATURE RANGE IT A)
-55 to +125
0
C
PACKAGE TYPES D. F. H
-40 to +85
0
C
PACKAGE TYPE E
-65 to + 150°C
STORAGE TEMPERATURE RANGE (T stg )
LEAD TEMPERATURE (DURING SOLDERING)
At distance
1/16
±
1/32
Inch (1 59 ± 0 79 mm) from case for lOs max
'0
INPUT VOLTAGE
(VI) -
V
20
Fig.
1 -
TVPlcal voltage transfer characteristics.
·
-
.
~
·
!l
IO~:
AMBIENT TEMPERATURE (T Al-25-C
2
"-
~10"8
I
II I
li
4l
_DYNAMIC ELECTRICAL CHARACTERISTICS
At TA
=
2!tC; Input
t
r•
tf=
20ns. C L
=
50pF. RL
=
200H1.
ALL TYPES
LIMITS
TYP.
MAX.
.
i
·
""
·
.
..
.
..
... ...
l5
~
~
2
10'
,.:-
. .&"Z/v
~~
.§.;j.t7
~:
;c
V
'...
IV
/ "
.-
//1/
I
2
2i
o
102
/ /.-
1/ .-
CL.~
pF
CL.15 pF _ .. -
2
'0
2
2
II I
2
I
'0
10 2
10'
INPUT FREQUENCY
(t
I
J -
kHt
'0'
TEST CONDITIONS
CHARACTERISTIC
V DD
VOLTS
Propagation Delay Time.
tpHL. tPLH
Transition Time.
tTHL. tTLH
Input Capacitance. CIN
Any Input
UNITS
Fig.2
-
TVPlcal power diSSipation vs. frequencv.
5
10
15
5
10
15
125
60
45
100
50
40
5
250
120
90
200
100
80
75
ns
ns
pF
~
DRAIN-lO-SOURCE VOLTAGE
(VoSI-V
Fig.
3 -
TVPlcal output low (sink) current
characteristics.
4 *1151
31111
5021~
6(10)
4031
. .
. .
&
Vss
VDD
*
LOGIC DIAGRAM
ALL INPUTS ARE
PROTECTED BY
COS/MDS PROTECTION
NETWORK
7
VSS
INVERTER AND I OF 2 GATES
(NUMBERS IN PARENTHESES ARE
TERMINAL NUMBERS FOR SECOND GATE 1
ORA,N-TO-SOURCE VOLTAGE (VOs)-V
FlgA
-
Schematic and logic diagrams for CD4000B.
F,g.5
-
Minimum output low (Sink)
current characteristics
51
CD4000B, CD4001 B, CD4002B, CD4025B Typ
s
1(a.6'13)~
2(9,',12)
LOGIC DIAGRAM
ORAIN- TO- SOURCE VOLTAGE (Vosl-"
(I~,4,1I)
(9';;,12)
J
Un
10F 4 GATES
(NUMBERS IN PARENTHESES
ARE TERM I NAL NUMBERS
FOR OTHER GATES)
*ALL INPUTS ARE PROTECTED BY
COS/MOO PROTECTION NETWORK
Yss
~f
Fig.9
-
Typical output high (source)
current characteristics.
ORAIN-TO-SOURCE IIOLrAGE (VDsl-V
Flg,6
-
Schematic and logic diagrams for CD40018,
2(12)~
3(11)
1(13)
4(10)
5(9)
LOGIC DIAGRAM
,II
(9)
IIALL INPUTS ARE PROTECTED BY
COS/MOS PROTECTION NETWORK
10F
2
GATES (NUMBERS IN
PARENTHESES ARE TERMINAL
NUMBERS FOR SECOND GATE)
&~
4(2,12)
5(B,13)
Fig. 10
-
Minimum output high (source)
current characteristics.
Fig.
7 -
Schematic and logic diagrams for CD40028.
3(1'II)~
6
(9,10)
LOGIC DIAGRAM
LOAD CAPACITANCE (CL)-pF
Fig.
11 -
Typical transition time vs. load
capacitance.
(2,12)
ROO
*
10F 3 GATES (NUMBERS IN
PARENTHESES ARE TERMINAL
NUMBERS FOR OTHER GATES)
5*
(B,13)
Y
ss
ALL INPUTS ARE PROTECTED
BY COS
I
MOS PROTECTION
NETWORK
LOAD CAPACIrANCE
(ct,I-
pF
Fig.8
-,
Schematic and logic diagrams for CD40258.
Fig.
12 -
TYPf(:al propagation delay time
vs. load capacitance.
52
CD4000B, CD4001B, CD4002B, CD4025B Types
INPUOS
Veo
Veo
NOTE
MEASURE INPUTS
SEQUENTIALLY.
TO BOTH Voo AND VSS
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo
DR
VSS
VSS
VIH
INPUTQVeo
OUTPUTS
o
Vss
o
~
Vss
~
v~
'-
VSS
~
~
NOTE
TEST ANY COMBINATION
OF INPUTS
'DO
Fig.
73 -'
Input leakage current
test circuit.
Fig.
74 -
Input-voltage
test CirCUit.
Fig.
75 -
QUiescent-deVice
current test circuit.
TERMINAL ASSIGNMENTS (TOP VIEW)
Ie
2
14
13
12
Voo
NC{
Ie
14
13
12
Voo
J
.A+ii+C+ij
Ie
2
14
13
12
Voo
Ie
2
14
13
12
Voo
F
E
II
10
K·m
K.ii"+E'+F
L'G
0
J·m
C
Vss
2
A
K'
E+'f+1i+H
F
K'O+E+F
VSS
G
II
10
M'G+H
L·{+F
10
II
10
L-G+H+I
JaA+S+C
H.A+m
Vss
9
B
NC
VSS
9
9
B
NC
e
C
92CS-24468RI
92CS-24447RI
NC-NO CONNECTION
He- NO CONNECTION
Ne. NO CONNECTION
He -NO CONNECTION
CD4000B
CD4001B
CHIP PHOTOGRAPHS
CD4002B
~ad
CD4025B
Dimensions and
Layouts 0
55-
4-10
0102-0254)
65-73
(1651-1854)
6!1-n
I 6!11-1 8!14
92CS-28908RI
I
l
J
57-65
52-60
(1320-1524)
CD4000B
CD4001B
40
50
I
eo
1.524
~iIIi~~J'651J
4-10
(0.102 - 0.254)
66-74
92C$- 28910RI
(1.676-1.880)
CD4025B
I
53
CD4002B
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