SRAM
Austin Semiconductor, Inc.
32K x 8 SRAM
SRAM MEMORY ARRAY
FEATURES
•
•
•
•
•
•
•
•
•
Access Times: 12, 15, & 20ns
Fast output enable (tDOE) for cache applications
Low active power: 400 mW (TYP)
Low power standby
Fully static operation, no clock or refresh required
High-performance, low-power CMOS double-metal process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\
All inputs and outputs are TTL compatible
AS5C2568
PIN ASSIGNMENT
(Top View)
28-PIN PSOJ (DJ)
OPTIONS
•
Timing
12ns access*
15ns access
20ns access
•
Package(s)**
Plastic SOJ
MARKING
-12
-15
-20
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 V
CC
27 WE\
26 A13
25 A8
24 A9
23 A11
22 OE\
21 A10
20 CE\
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
DJ
No. 906
•
Operating Temperature Ranges
Military -55
o
C to +125
o
C
Industrial -40
o
C to +85
o
C
XT
IT
*
-12 available in IT only.
**
For ceramic version of this product, see the MT5C2568
data sheet.
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs using a four-transistor
memory cell. These SRAMs are fabricated using double-layer
metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, Aus-
tin Semiconductor offers chip enable (CE\) and output enable
(OE\) capability. These enhancements can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The device offers a reduced power standby mode when dis-
abled. This allows system designs to achieve low standby
power requirements.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
A0
Vcc
AS5C2568
DECODER
256 x 1024
MEMORY ARRAY
GND
A14
I/O0
I/O
DATA
CIRCUIT
I/O7
COLUMN I/O
9A128-1
CE\
OE\
CONTROL
CIRCUIT
WE\
TRUTH TABLE
MODE
STANDBY
READ
READ
WRITE
OE\
X
L
H
X
CE\
H
L
L
L
WE\
X
H
H
L
DQ
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Input or DQ Relative
to Vss..................................................................-0.5V to Vcc +0.5V
Voltage on Vcc Supply Relative to Vss.......................-1V to +7V
Storage Temperature..............................................-65
o
C to +150
o
C
Power Dissipation.......................................................................1W
Short Circuit Output Current............................................20mA
Lead Temperature (soldering 10 seconds)........................+260
o
C
Max. Junction Temperature.................................................+175
o
C
AS5C2568
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C or -40
o
C to +85
o
C; V
CC
= 5.0V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
CONDITIONS
SYMBOL
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
MIN
2.2
-0.5
-5
-5
2.4
MAX
Vcc+0.5
0.8
5
5
0.4
UNITS
V
V
µA
µA
V
V
1
1
NOTES
1
1, 2
0V
≤
V
IN
≤
Vcc
Output(s) disabled
0V < V
OUT
< Vcc
I
OH
= -4.0mA
I
OL
= 8.0mA
!
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( ' ) * +
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2
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( 3 2
& '
4 '
5 ' ) * +
, ) 67
*
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4'
89'( , ) 67
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
AS5C2568
Rev. 2.0 12/00
CONDITIONS
T
A
= 25
o
C, f = 1MHz
Vcc = 5V
SYM
C
IN
C
IO
MAX
8
10
UNITS
pF
pF
NOTES
4
4
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
AS5C2568
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C or -40
o
C to +85
o
C; V
CC
= 5.0V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in Low-Z
Chip disable to output in High-Z
Chip enable to power-up time
Chip disable to power-down time
Output enable to access time
Output enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write enable to output in High-Z
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
12
9
9
0
0
10
7
0
2
0
7
15
10
10
0
0
12
8
0
2
0
7
20
12
12
0
0
15
10
0
2
0
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
6, 7
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
0
6
0
12
6
0
7
2
2
7
0
15
7
0
8
12
12
12
2
2
8
0
20
8
15
15
15
2
2
9
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
7
6, 7
4
4
SYM
-12
MIN
MAX
-15
MIN MAX
-20
MIN
MAX
UNITS NOTES
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels....................................................Vss to 3V
Input rise and fall times.....................................................5ns
Input timing reference level.............................................1.5V
Output reference level......................................................1.5V
Output load.................................................See figures 1 & 2
+5V
480
Q
255
30 pF
Q
255
Fig. 2
OUTPUT LOAD
EQUIVALENT
5 pF
AS5C2568
+5V
480
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates. The
specified value applies with the outputs unloaded, and
f=
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading as
shown in Fig. 1 unless otherwise noted.
t
HZCE,
t
HZOE and
t
HZWE are specified with CL = 5pF
as in Fig. 2. Transition is measured ±500mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7.
Fig. 1
OUTPUT LOAD
EQUIVALENT
4.
5.
6.
At any given temperature and voltage condition,
t
HZCE
is less than
t
LZCE, and
t
HZWE is less than
t
LZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CONDITIONS
SYMBOL
V
DR
I
CCDR
V
CC
= 2V
V
CC
= 3V
t
MIN
2
Data Retention Current
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
MAX
--
1.0
2.0
UNITS
V
mA
mA
ns
NOTES
Chip Deselect to Data
Retention Time
Operation Recovery Time
CDR
t
0
--
t
4
4, 11
R
RC
ns
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
DATA RETENTION MODE
4.5V
CDR
V
DR
V
DR
> 2V
4.5V
t
R
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
4321
4321
4321
4321
321
21
321
321
3
CE\
V
IH
V
IL
321
876
32154321
4325
876
43254321
32114321
876
42214321
32114321
876
3311
4325
8765
87654321
21
21
87654321
321
87654321
321
21
87654321
321
21
87654321
DON’T CARE
UNDEFINED
Embedded System
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