AT52BR6408A datasheet, PDF - EEWORLD Datasheet

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AT52BR6408A: Description64-Mbit Flash, 8-Mbit SRAM (x16 I/O); File Size247KB，37 Pages; ManufacturerAtmel (Microchip)

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AT52BR6408A Overview

64-Mbit Flash, 8-Mbit SRAM (x16 I/O)

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Stack Module Features

•

64-Mbit Flash + 8-Mbit SRAM

Power Supply of 2.7V to 3.1V

Data I/O x16

66-ball CBGA Package

64-Mbit Flash Features

•

64-megabit (4M x 16) Flash Memory

•

2.7V - 3.1V Read/Write

•

High Performance

•

– Asynchronous Access Time – 70, 85 ns

Sector Erase Architecture

– Eight 4K Word Sectors with Individual Write Lockout

– 32K Word Main Sectors with Individual Write Lockout

Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms

64M, Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not

Being Programmed/Erased

– Memory Plane A: 16M of Memory Including Eight 4K Word Sectors

– Memory Plane B: 16M of Memory Consisting of 32K Word Sectors

– Memory Plane C: 16M of Memory Consisting of 32K Word Sectors

– Memory Plane D: 16M of Memory Consisting of 32K Word Sectors

Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming Data from Any Sector by Suspending Erase

of a Different Sector

– Supports Reading Any Word by Suspending Programming of Any Other Word

Low-power Operation

– 30 mA Active

– 10 µA Standby

1.8V I/O Option Reduces Overall System Power

Data Polling and Toggle Bit for End of Program Detection

VPP Pin for Write Protection and Accelerated Program/Erase Operations

RESET Input for Device Initialization

Top or Bottom Boot Block Configuration Available

128-bit Protection Register

Common Flash Interface (CFI)

64-Mbit Flash,

8-Mbit SRAM

(x16 I/O)

AT52BR6408A

AT52BR6408AT

Preliminary

•

8-Mbit SRAM Features

•

8-Mbit (512K x 16)

2.7V to 3.1V V

Operation

70 ns Access Time

Low-power

– 2 mA Typical (Active)

– 1 µA Typical (Standby)

•

Industrial Temperature Range

Stack Module Description

The AT52BR6408A(T) consists of a 64-Mbit Flash stacked with an 8-Mbit SRAM in a

single CBGA package.

Stack Module Memory Contents

Device

AT52BR6408A(T)

Memory Combination

64M Flash + 8M SRAM

Flash Read Access

Asynchronous, Page Mode

Rev. 3425A–STKD–1/04

AT52BR6408A(T)

64-Mbit Flash

Description

The 64-Mbit Flash memory is divided into multiple sectors and planes for erase opera-

tions. The devices can be read or reprogrammed off a single 2.7V power supply, making

them ideally suited for in-system programming.

The 64-Mbit device is divided into four memory planes. A read operation can occur in

any of the three planes which is not being programmed or erased. This concurrent oper-

ation allows improved system performance by not requiring the system to wait for a

program or erase operation to complete before a read is performed. To further increase

the flexibility of the device, it contains an Erase Suspend and Program Suspend feature.

This feature will put the erase or program on hold for any amount of time and let the user

read data from or program data to any of the remaining sectors. There is no reason to

suspend the erase or program operation if the data to be read is in another memory

plane. The end of program or erase is detected by Data Polling or toggle bit.

The VPP pin provides data protection and faster programming and erase times. When

the V

input is below 0.8V, the program and erase functions are inhibited. When V

at 1.65V or above, normal program and erase operations can be performed. With V

12.0V, the program and erase operations are accelerated.

With V

at 12V, a six-byte command (Enter Single Pulse Program Mode) to remove the

requirement of entering the three-byte program sequence is offered to further improve

programming time. After entering the six-byte code, only single pulses on the write con-

trol lines are required for writing into the device. This mode (Single Pulse Word

Program) is exited by powering down the device, by taking the RESET pin to GND or by

a high-to-low transition on the V

input. Erase, Erase Suspend/Resume, Program Sus-

pend/Resume and Read Reset commands will not work while in this mode; if entered

they will result in data being programmed into the device. It is not recommended that the

six-byte code reside in the software of the final product but only exist in external pro-

gramming code.

Device Operation

COMMAND SEQUENCES:

The device powers on in the read mode. Command

sequences are used to place the device in other operating modes such as program and

erase. After the completion of a program or an erase cycle, the device enters the read

mode. The command sequences are written by applying a low pulse on the WE input

with CE low and OE high or by applying a low-going pulse on the CE input with WE low

and OE high. The address is latched on the falling edge of the WE or CE pulse which-

ever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,

whichever occurs first. The addresses used in the command sequences are not affected

by entering the command sequences.

ASYNCHRONOUS READ:

The 64-Mbit Flash is accessed like an EPROM. When CE

and OE are low and WE is high, the data stored at the memory location determined by

the address pins are asserted on the outputs. The outputs are put in the high impedance

state whenever CE or OE is high. This dual-line control gives designers flexibility in pre-

venting bus contention.

RESET:

A RESET input pin is provided to ease some system applications. When

RESET is at a logic high level, the device is in its standard operating mode. A low level

on the RESET pin halts the present device operation and puts the outputs of the device

in a high-impedance state. When a high level is reasserted on the RESET pin, the

device returns to read or standby mode, depending upon the state of the control pins.

3425A–STKD–1/04

ERASE:

Before a word can be reprogrammed it must be erased. The erased state of

the memory bits is a logical “1”. The entire memory can be erased by using the Chip

Erase command or individual planes or sectors can be erased by using the Plane Erase

or Sector Erase commands.

CHIP ERASE:

Chip Erase is a six-bus cycle operation. The automatic erase begins on

the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected

sectors. After the full chip erase the device will return back to the read mode. The hard-

ware reset during Chip Erase will stop the erase but the data will be of unknown state.

Any command during Chip Erase except Erase Suspend will be ignored.

PLANE ERASE:

As a alternative to a full chip erase, the device is organized into four

planes that can be individually erased. The plane erase command is a six-bus cycle

operation. The plane whose address is valid at the sixth falling edge of WE will be

erased provided none of the sectors within the plane are protected.

SECTOR ERASE:

As an alternative to a full chip erase or a plane erase, the device is

organized into multiple sectors that can be individually erased. The Sector Erase com-

mand is a six-bus cycle operation. The sector whose address is valid at the sixth falling

edge of WE will be erased provided the given sector has not been protected.

WORD PROGRAMMING:

The device is programmed on a word-by-word basis. Pro-

gramming is accomplished via the internal device command register and is a four-bus

cycle operation. The programming address and data are latched in the fourth cycle. The

device will automatically generate the required internal programming pulses. Please

note that a “0” cannot be programmed back to a “1”; only erase operations can convert

“0”s to “1”s.

FLEXIBLE SECTOR PROTECTION:

The 64-Mbit device offers two sector protection

modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protec-

tion for sectors whose content changes frequently. The Hardlock protection mode is

recommended for sectors whose content changes infrequently. Once either of these two

modes is enabled, the contents of the selected sector is read-only and cannot be erased

or programmed. Each sector can be independently programmed for either the Softlock

or Hardlock sector protection mode. At power-up and reset, all sectors have their Soft-

lock protection mode enabled.

SOFTLOCK AND UNLOCK:

The Softlock protection mode can be disabled by issuing a

two-bus cycle Unlock command to the selected sector. Once a sector is unlocked, its

contents can be erased or programmed. To enable the Softlock protection mode, a six-

bus cycle Softlock command must be issued to the selected sector.

HARDLOCK AND WRITE PROTECT (WP):

The Hardlock sector protection mode oper-

ates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection

mode can be enabled by issuing a six-bus cycle Hardlock software command to the

selected sector. The state of the Write Protect pin affects whether the Hardlock protec-

tion mode can be overridden.

• When the WP pin is low and the Hardlock protection mode is enabled, the sector

cannot be unlocked and the contents of the sector is read-only.

• When the WP pin is high, the Hardlock protection mode is overridden and the sector

can be unlocked via the Unlock command.

AT52BR6408A(T)

3425A–STKD–1/04

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