converter with voltage output operational amplifier.
Fast current switches and laser-trimmed thin-film
resistors provide a highly accurate, fast D/A con-
verter.
Digital interfacing is facilitated by a double buffered
latch. The input latch consists of one 8-bit byte and
one 4-bit nibble to allow interfacing to 8-bit (right
justified format) or 16-bit data buses. Input gating
logic is designed so that the last nibble or byte to be
loaded can be loaded simultaneously with the transfer
of data to the D/A latch saving computer instructions.
A reset control allows the DAC813 D/A latch to
asynchronously reset the D/A output to bipolar zero,
a feature useful for power-up reset, recalibration, or
for system re-initialization upon system failure.
The DAC813 is specified to
±1/2LSB
maximum lin-
earity error (J, A grades) and
±1/4LSB
(K grade).
It is packaged in 28-pin 0.3" wide plastic DIP and
28-lead plastic SOIC
DESCRIPTION
The DAC813 is a complete monolithic 12-bit digital-
to-analog converter with a flexible digital interface.
It includes a precision +10V reference, interface con-
trol logic, double-buffered latch and a 12-bit D/A
Reset
4 MSBs
8 LSBs
Input Latch
4
Input Latch
8
24.9kΩ
BPO
20V Span
25kΩ
D/A Latch
20V Span
12
10V
Reference
12-Bit D/A
Converter
25kΩ
49.5kΩ
V
REF OUT
V
REF IN
V
OUT
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
NOTES: (1) USB = Unipolar Straight Binary; BOB = Bipolar Offset Binary. (2) TTL and 5V CMOS compatible. (3) Open DATA input lines will be pulled above +5.5V.
See discussion under LOGIC INPUT COMPATIBILITY in the OPERATION section. (4) Specified with 500Ω Pin 6 to 7. Adjustable to zero with external trim
potentiometer. (5) Error at input code 000
HEX
for unipolar mode, FSR = 10V. (6) Error at input code 800
HEX
for bipolar range. Specified with 100Ω Pin 6 to 4 and
with 500Ω pin 6 to 7. See page 9 for zero adjustment procedure. (7) FSR means Full Scale Range and is 20V for the
±10V
range. (8) Maximum represents the
3σ limit. Not 100% tested for this parameter. (9) At the major carry, 7FF
HEX
to 800
HEX
and 800
HEX
to 7FF
HEX
. (10) The maximum voltage at which ACOM and DCOM
may be separated without affecting accuracy specifications.
±V
CC
>
±11.4V
±V
CC
>
±11.4V
At DC
CONDITIONS
MIN
TYP
MAX
12
USB, BOB
+2
0
V
IN
= +2.7V
V
IN
= +0.4V
±1/4
±1/2
±0.05
±0.01
±0.02
Guaranteed
5
1
±5
±1
±3
±1/2
Guaranteed
+5.5
+0.8
±10
±10
T
T
T
T
T
T
T
VDC
VDC
µA
µA
MIN
DAC813KP, KU
TYP
MAX
T
UNITS
Bits
±1/2
±3/4
±0.2
±0.02
±0.2
10
10
±30
±3
±10
±3/4
20V Range
Over Specification
Temperature Range
±1/8
±1/4
T
T
T
T
T
T
T
T
T
±1/4
T
±1/4
±1/2
T
T
T
T
T
±15
±3
±5
±1/2
LSB
LSB
%
% of FSR
(7)
% of FSR
ppm of FSR/%
ppm of FSR/%
ppm/°C
ppm of FSR/°C
ppm of FSR/°C
LSB
20V Range
10V Range
4.5
3.3
2
10
0 to +10
±5, ±10
6
5
T
T
T
T
T
T
T
T
T
T
T
µs
µs
µs
V/µs
V
V
mA
Ω
±5
0.2
Indefinite
+9.95
5
+10
2
±5
Indefinite
+11.4
–11.4
+15
–15
13
–5
270
0
–40
–40
–55
–60
–65
+10.05
T
T
T
T
T
T
T
±25
T
V
mA
Ω
ppm/°C
No Load
No Load
–3
+16.5
–16.5
15
–7
+3
330
+70
+85
+85
+125
+100
+150
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
VDC
VDC
mA
mA
V
mW
°C
°C
°C
°C
°C
°C
T
T
T
T
T
T
®
DAC813
2
PIN DESCRIPTIONS
PIN
1
2, 3
4
NAME
+V
L
20V Range
BPO
DESCRIPTION
Positive supply pin for logic circuits. Connect to +V
CC
.
Connect Pin 2 or Pin 3 to Pin 9 (V
OUT
) for a 20V
FSR. Connect both to Pin 9 for a 10V FSR.
Bipolar offset. Connect to Pin 6 (V
REF OUT
) through
100Ω resistor or 200Ω potentiometer for bipolar
operation.
Analog common,
±V
CC
supply return.
+10V reference output referred to ACOM.
Connected to V
REF OUT
through a 1kΩ gain
adjustment potentiometer or a 500Ω resistor.
Analog supply input, nominally +12V to +15V
referred to ACOM.
D/A converter voltage output.
Analog supply input, nominally –12V or –15V
referred to ACOM.
Master enable for LDAC, LLSB, and LMSB. Must
be low for data transfer to any latch.
Load DAC. Must be low with WR for data transfer
to the D/A latch and simultaneous update of the
D/A converter.
When low, resets the D/A latch such that a Bipolar
Zero output is produced. This control overrides all
other data input operations.
Enable for 4-bit input latch of D
8
-D
11
data inputs.
NOTE: This logic path is slower than the WR path.
Enable for 8-bit input latch of D
0
-D
7
data inputs.
NOTE: This logic path is slower than the WR path.
Digital common.
Data Bit 1, LSB.
Data Bit 2.
Data Bit 3.
Data Bit 4.
Data Bit 5.
Data Bit 6.
Data Bit 7.
Data Bit 8.
Data Bit 9.
Data Bit 10.
Data Bit 11.
Data Bit 12, MSB, positive true.
ABSOLUTE MAXIMUM RATINGS
(1)
+V
CC
to ACOM .......................................................................... 0 to +18V
–V
CC
to ACOM .......................................................................... 0 to –18V
+V
CC
to –V
CC
............................................................................ 0 to +36V
DCOM with respect to ACOM .............................................................
±4V
Digital Inputs (Pins 11–15, 17–28) to DCOM .................... –0.5V to +V
CC
External Voltage Applied to BPO Span Resistor ..............................
±V
CC
V
REF OUT
........................................................... Indefinite Short to ACOM
V
OUT
................................................................. Indefinite Short to ACOM
Power Dissipation .......................................................................... 750mW
Lead Temperature (soldering, 10s) ............................................... +300°C
Max Junction Temperature ............................................................ +165°C
Thermal Resistance,
θ
J-A
:Plastic DIP and SOIC ........................ 130°C/W
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
5
6
7
8
9
10
11
12
ACOM
V
REF OUT
V
REF IN
+V
CC
V
OUT
–V
CC
WR
LDAC
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
13
Reset
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
LMSB
LLSB
DCOM
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
(1)
246
217
246
217
217
TEMPERATURE
RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
LINEARITY
ERROR, MAX
AT +25
°
C (LSB)
±1/2
±1/2
±1/4
±1/4
±1/2
GAIN
DRIFT
(ppm/
°
C)
±30
±30
±15
±15
±30
PRODUCT
DAC813JP
DAC813JU
DAC813KP
DAC813KU
DAC813AU
PACKAGE
28-Pin Plastic DIP
28-Lead Plastic SOIC
28-Pin Plastic DIP
28-Lead Plastic SOIC
28-Lead Plastic SOIC
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
DAC813
MINIMUM TIMING DIAGRAMS
WRITE CYCLE #1
(Load first rank from Data Bus: LDAC = 1)
> 50ns
LLSB, LMSB
> 50ns
DB11–DB0
>5ns
WR
> 50ns
WRITE CYCLE #2
(Load second rank from first rank: LLSB, LMSB = 1)
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