NXP Semiconductors
Technical Data
MC33910G5AC/MC3433910G5AC
Document Number: MC33911
Rev. 10.0, 7/2016
LIN system basis chip with DC motor
pre-driver
The 33911G5/BAC is a SMARTMOS Serial Peripheral Interface (SPI) controlled
System Basis Chip (SBC), combining many frequently used functions in an MCU
based system, plus a Local Interconnect Network (LIN) transceiver. The 33911
has a 5.0 V, 50 mA/60 mA low dropout regulator with full protection and reporting
features. The device provides full SPI readable diagnostics and a selectable
timing watchdog for detecting errant operation. The LIN Protocol Specification
2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry which can be
disabled for higher data rates.
One 50 mA/60 mA high-side switch and two 150 mA/160 mA low-side switches
with output protection are available. All outputs can be pulse-width modulated
(PWM). Two high-voltage inputs are available for use in contact monitoring, or
as external wake-up inputs. These inputs can be used as high-voltage Analog
Inputs. The voltage on these pins is divided by a selectable ratio and available
via an analog multiplexer.
The 33911 has three main operating modes: Normal (all functions available),
Sleep (V
DD
off, wake-up via LIN, wake-up inputs (L1, L2), cyclic sense, and
forced wake-up), and Stop (V
DD
on with limited current capability, wake-up via
CS, LIN bus, wake-up inputs, cyclic sense, forced wake-up, and external reset).
The 33911 is compatible with LIN Protocol Specification 2.0, 2.1, and
SAEJ2602-2.
Features
• Full-duplex SPI interface at frequencies up to 4.0 MHz
• LIN transceiver capable of up to 100 kbps with wave shaping
• One 50 mA/60 mA high-side and two 150 mA/60 mA low-side protected
switches
• Two high-voltage analog/logic Inputs
• Configurable window watchdog
• 5.0 V low drop regulator with fault detection and low-voltage reset (LVR)
circuitry
33911
SYSTEM BASIS CHIP WITH LIN
AC SUFFIX (Pb-FREE)
98ASH70029A
32-PIN LQFP
Applications
• Window lift
• Mirror switch
• Door lock
• Sunroof
• Light control
V
BAT
33911
VS1
VS2
VSENSE
HS1
L1
L2
LIN INTERFACE
LIN
VDD
PWMIN
ADOUT0
LS1
M
MCU
MOSI
MISO
SCLK
CS
RXD
TXD
IRQ
RST
LS2
WDCONF
LGND
PGND
AGND
Figure 1. 33911 simplified application diagram
© 2016 NXP B.V.
1
Orderable parts
The 33911G5 data sheet is within
MC33911G5 product specifications - page 3 to page 52.
The 33911BAC data sheet is within
MC33911BAC product specifications - page 53 to page 100.
Table 1. Orderable part variations
Device
MC33911G5AC/R2
Temperature
- 40 °C to 125 °C
Package
Generation
• Increase ESD GUN IEC61000-4-2 (gun test contact with 150 pF, 330
Ω
test conditions) performance to achieve
±6.0
kV min on the LIN pin.
• Immunity against ISO7637 pulse 3b
• Reduce EMC emission level on LIN
• Improve EMC immunity against RF – target new specification including 3
x 68 pF
• Comply with J2602 conformance test
Initial release
MC34911G5AC/R2
- 40 °C to 85 °C
2.5
32-LQFP
MC33911BAC/R2
MC34911BAC/R2
- 40 °C to 125 °C
- 40 °C to 85 °C
2.0
33911
2
NXP Semiconductors
4
4.1
Pin connections
Pinout diagram
VSENSE
AGND
VDD
NC*
NC*
27
26
32
31
RXD
TXD
MISO
MOSI
SCLK
CS
ADOUT0
PWMIN
1
2
3
4
5
6
7
8
* See Recommendation in Table below
25
29
30
28
HS1
VS1
VS2
24
23
22
21
20
19
18
17
NC*
L1
L2
NC*
NC*
LS1
PGND
LS2
10
IRQ
11
12
13
14
15
16
NC*
NC*
RST
WDCONF
Figure 3. 33911 pin connections
4.2
Pin definitions
A functional description of each pin can be found in the
Functional pin description
section beginning on
page 23.
Table 2. 33911 Pin definitions
Pin
1
2
3
4
5
6
7
8
Pin name
RXD
TXD
MISO
MOSI
SCLK
CS
ADOUT0
PWMIN
Formal name
Receiver Output
Transmitter Input
SPI Output
SPI Input
SPI Clock
SPI Chip Select
Analog Output Pin 0
PWM Input
Definition
This pin is the receiver output of the LIN interface which reports the state of the bus
voltage to the MCU interface.
This pin is the transmitter input of the LIN interface which controls the state of the bus
output.
SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the high-
impedance state.
SPI (Serial Peripheral Interface) data input.
SPI (Serial Peripheral Interface) clock Input.
SPI (Serial Peripheral Interface) chip select input pin. CS is active low.
Analog multiplexer output.
High-side and low-side pulse width modulation input.
LGND
NC*
LIN
9
33911
NXP Semiconductors
5
京公网安备 11010802033920号
EEWORLD
