#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25
_
C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in
µA
(per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
‡VH = VT+ – VT– (But maximum variation of VH is specified as less than VT + max – VT – min).
MC14584B
2
MOTOROLA CMOS LOGIC DATA
Vout , OUTPUT VOLTAGE (Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(CL = 50 pF, TA = 25
_
C)
Characteristic
Symbol
tTLH
VDD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
Min
—
—
—
—
—
—
—
—
—
Typ #
100
50
40
100
50
40
125
50
40
Max
200
100
80
200
100
80
250
100
80
Unit
ns
Output Rise Time
Output Fall Time
tTHL
ns
Propagation Delay Time
tPLH, tPHL
ns
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
PULSE
GENERATOR
VDD
14
OUTPUT
INPUT
7 VSS
CL
20 ns
INPUT
90%
50%
10%
90%
50%
10%
tf
tr
tPLH
20 ns
VDD
VSS
VOH
VOL
tPHL
OUTPUT
Figure 1. Switching Time Test Circuit and Waveforms
Vin
VH
Vin
VDD
VT+
VT–
VSS
VDD
Vout
VSS
Vout
VSS
Vin
Vout
VH
VDD
VT+
VT–
VSS
VDD
(a) Schmitt Triggers will square up inputs with slow
rise and fall times.
(b) A Schmitt trigger offers maximum noise immunity
in gate applications.
Figure 2. Typical Schmitt Trigger Applications
VDD
PIN ASSIGNMENT
IN 1
OUT 1
IN 2
OUT 2
IN 3
OUT 3
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
IN 6
OUT 6
IN 5
OUT 5
IN 4
OUT 4
0
0
VT–
VH
VT+
VDD
Vin, INPUT VOLTAGE (Vdc)
Figure 3. Typical Transfer Characteristics
MOTOROLA CMOS LOGIC DATA
MC14584B
3
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES
MIN
MAX
0.750
0.785
0.245
0.280
0.155
0.200
0.015
0.020
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
_
15
_
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.94
6.23
7.11
3.94
5.08
0.39
0.50
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
_
15
_
0.51
1.01
–A–
14
9
–B–
1
7
C
L
–T–
SEATING
PLANE
K
F
D
14 PL
G
0.25 (0.010)
M
N
J
T A
S
14 PL
M
0.25 (0.010)
M
T B
S
DIM
A
B
C
D
F
G
J
K
L
M
N
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
8
B
1
7
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0
_
10
_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0
_
10
_
0.39
1.01
A
F
C
N
H
G
D
SEATING
PLANE
L
J
K
M
MC14584B
4
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
–A–
14
8
–B–
1
7
P
7 PL
0.25 (0.010)
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
C
R
X 45
_
F
–T–
SEATING
PLANE
D
14 PL
0.25 (0.010)
M
K
T B
S
M
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
_
7
_
0.228
0.244
0.010
0.019
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