MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC145532/D
ADPCM Transcoder
MC145532
16
1
Conforms to G.721–1988 and T1.301–1987
The MC145532 Adaptive Differential Pulse Code Modulation (ADPCM)
Transcoder provides a low–cost, full–duplex, single–channel transcoder to
(from) a 64 kbps PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or
64 kbps channel.
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Complies with CCITT Recommendation G.721–1988
Complies with the American National Standard (T1.301–1987)
Full–Duplex, Single–Channel Operation
Mu–Law or A–Law Coding is Pin Selectable
Synchronous or Asynchronous Operation
Easily Interfaces with Any Member of Motorola’s PCM Codec–Filter
Mono–Circuit Family or Other Industry Standard Codec
Serial PCM and ADPCM Data Transfer Rate from 64 kbps to 5.12 Mbps
Power–Down Capability for Low Current Consumption
The Reset State, an Option Specified in the Standards, is Automatically
Initiated When the RESET Pin is Released
Simple Time Slot Assignment Timing for Transcoder Applications
Single 5 V Power Supply
16–Pin Package
The MC145536EVK is the Evaluation Platform for the MC145532 and Also
Includes the MC145480 5 V PCM Codec–Filter
DW SUFFIX
SOG PACKAGE
CASE 751G
16
1
L SUFFIX
CERAMIC PACKAGE
CASE 620
ORDERING INFORMATION
MC145532DW SOG Package
MC145532L
Ceramic Package
PIN ASSIGNMENT
MODE
DDO
DOE
DDC
DDI
DIE
RESET
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
EDO
EOE
EDC
EDI
EIE
SPC
APD
BLOCK DIAGRAM
DDO
DOE
S REG
DDC
DDI
DIGITAL
SIGNAL
PROCESSOR
REG
LATCH
S REG
EDC
EDI
I/O DATA BUS
EDO
EDE
S REG
DIE
LATCH
REG
S REG
EIE
MODE
APD
VSS
RESET
SPC
VDD
REV 1
9/95 (Replaces NP470)
©
Motorola, Inc. 1995
MOTOROLA
MC145532
1
DEVICE DESCRIPTION
An Adaptive Differential PCM (ADPCM) transcoder is used
to reduce the data rate required to transmit a PCM encoded
voice signal while maintaining the voice fidelity and intelli-
gibility of the PCM signal.
The transcoder is used on 64 kbps data streams which
represent either voice or voice band data signals that have
been digitized by a codec (e.g., MC145557). The transcoder
uses a filter to attempt to predict the next PCM input value
based on previous PCM input values. The error between the
predicted and the true PCM input value is the information
that is sent to the other end of the line. Hence the word differ-
ential, since the ADPCM data stream is the difference be-
tween the true PCM input value and the predicted value. The
term “adaptive” applies to the filter that is performing the pre-
diction. It is adaptive in that its transfer function changes
based on the PCM input data. That is, it adapts to the statis-
tics of the signals presented to it.
DECODER INPUT
DDI
Decoder Data Input (Pin 5)
ADPCM data to be decoded are applied to this input pin,
which operates in conjunction with DDC and DIE to enter the
data in a serial format.
DDC
Decoder Data Clock (Pin 4)
Data applied to DDI are latched into the transcoder on the
falling edge of DDC and data are output from DDO on the ris-
ing edge of DDC. The frequency of DDC may be as low as
64 kHz or as high as 5.12 MHz.
DIE
Decoder Input Enable (Pin 6)
The beginning of a new ADPCM word is indicated by a ris-
ing edge applied to this input. Data are serially clocked into
DDI on the subsequent falling edges of DDC following the
DIE rising edge. The frequency of DIE may not exceed
8 kHz.
DECODER OUTPUT
DDO
Decoder Data Output (Pin 2)
PCM data are available in a serial format from this output,
which operates in conjunction with DDC and DOE. DDO is a
three–state output that remains at a high–impedance state
except when presenting data.
DOE
Decoder Output Enable (Pin 3)
Each ADPCM word is requested by a rising edge on this
input which causes the DDO pin to provide the data when
clocked by DDC. One DOE must occur for each DIE.
CONTEXT
PIN DESCRIPTIONS
ENCODER INPUT
EDI
Encoder Data Input (Pin 12)
PCM data to be encoded are applied to this input pin which
operates synchronously with EDC and EIE to enter the data
in a serial format.
EDC
Encoder Data Clock (Pin 13)
Data applied to EDI are latched into the transcoder on a
falling edge of EDC and data are output from EDO on a rising
edge of this input pin. The frequency of EDC may be as low
as 64 kHz or as high as 5.12 MHz.
EIE
Encoder Input Enable (Pin 11)
The beginning of a new PCM word is indicated to the
transcoder by a rising edge applied to this input. The fre-
quency of EIE may not exceed 8 kHz.
ENCODER OUTPUT
EDO
Encoder Data Output (Pin 15)
ADPCM data are available in a serial format from this out-
put, which operates synchronously with EDC and EOE. EDO
is a three–state output which remains in a high–impedance
state, except when presenting data.
EOE
Encoder Output Enable (Pin 14)
Each ADPCM word is requested by a rising edge on this
input, which causes the EDO pin to provide the data when
clocked by EDC. One EOE must occur for each EIE.
MODE
Mode Select (Pin 1)
A logic 0 applied to this input makes the transcoder com-
patible with Mu–255 companding and D3 data format. A
logic 1 applied to this pin makes the transcoder compatible
with A–Law companding with even bit inversion data format.
SPC
Signal Processor Clock (Pin 10)
This input is typically clocked with a 20.48 MHz clock sig-
nal which is used as the digital signal processor master
clock. This pin has a CMOS compatible input.
RESET
Reset (Pin 7)
A logic 0 applied to this input forces the transcoder into a
low power dissipation mode. A rising edge on this pin causes
power to be restored and the optional transcoder RESET
state (specified in the standards) to be forced. Valid data is
available at the output pins four input enables after a rising
edge on this pin. This pin has a CMOS compatible input.
MC145532
2
MOTOROLA
APD
Absolute Power Down (Pin 9)
A logic 1 applied to this input forces the transcoder into a
power saving mode. This pin has a CMOS compatible input.
POWER SUPPLY
VDD
Positive Power Supply (Pin 16)
The most positive power supply pin, normally 5 V.
VSS
Negative Power Supply (Pin 8)
The most negative power supply pin, normally 0 V.
Note that only a 32 kbps encoding rate can be specified
when using short frame mode on the encoder input.
ENCODER INPUT — LONG FRAME
Figure 2 shows the clock, enable, and data signals for the
encoder input in long frame mode. In this mode, the data is
captured by the MC145532 on the falling edge of EDC.
The determination of the encoding rate is made based on
the number of falling EDC edges seen by the MC145532
while EIE is high. Four edges implies a 32 kbps encoding
rate, three edges implies a 24 kbps encoding rate, two edges
implies a 16 kbps rate, and from five to eight inclusive imply
a 64 kbps rate. The encoding rate may be changed on a
frame–by–frame basis. The encoded word is available at
EDO (via EOE and EDC) from 250
µs
to 375
µs
after it is re-
quested.
ENCODER OUTPUT — SHORT FRAME
Figure 3 shows the timing of the encoder output in short
frame mode. The length of the LSB is always one half of an
EDC cycle.
The EDO will provide the correct number of bits for the en-
coding rate that was selected for this frame of data on the
encoder input pins. The data is loaded into the MC145532
during one frame, encoded on the next frame, and read dur-
ing the third frame.
ENCODER OUTPUT — LONG FRAME
Figure 4 shows the timing of the encoder output in long
frame mode. The enable must be wider than two falling
edges of the EDC to be in long frame mode. If the enable falls
before the correct number of bits have been presented to the
output (EDO), the transcoder will complete the presentation
of the bits to the output with the LSB being one half of an
EDC period wide. If the enable falls after the one half EDC
period of the LSB, then the LSB will be extended up to the full
EDC clock period and the subsequent data will be a recircu-
lation of the previous data, which repeats until the enable pin
falls. This is shown on the second enable for the 16 kbps en-
coding rate example in Figure 4.
DECODER INPUT — SHORT FRAME
Figure 5 shows the timing of the decoder data clock, the
decoder input enable, and the decoder data input pins in
short frame operation. Note that in this mode only a 32 kbps
decoding rate can be selected.
DECODER INPUT — LONG FRAME
Figure 6 shows the clock, enable, and data signals for the
decoder input in long frame mode.
The determination of the decoding rate is made based on
the number of falling DDC edges seen by the MC145532
while DIE is high. Four edges implies a 32 kbps decoding
rate, three edges implies a 24 kbps decoding rate, two edges
implies a 16 kbps rate, and from five to eight edges inclusive
imply a 64 kbps rate. The decoding rate may be changed on
a frame–by–frame basis.
FUNCTIONAL DESCRIPTION
ENCODING/DECODING RATES
The MC145532 allows for the encoding and decoding of
data at one of four rates on a sample–by–sample basis.
Each data sample that is provided to the part is accompanied
by an indication of the rate at which it is to be encoded or
decoded. The width of the enable pulse determines the
encoding/decoding rate chosen for each sample.
The 64 kbps rate allows for PCM data to be passed directly
through the part. The 32 kbps rate is either the G.721–1988
or the T1.301–1987 standard, depending on the state of the
mode pin. The 24 kbps encoding rate is compliant with
CCITT G.723–1988 and G.726. The 16 kbps rate is a modi-
fied quantizer from the 32 kbps technique and is not a stan-
dard.
TIMING
Figures 1 through 8 show the timing of the input and output
pins. The MC145532 determines the mode of the timing sig-
nals, either short or long frame, for each enable, independent
of the mode of any previous enables. A transition from short
frame to long frame mode or vice versa will cause at least
one frame of data to be destroyed. Each of the four sets of
I/O pins determines its mode independent of the other sets.
Thus the encoder input could be operating with long frame
timing and the output could be operating with short frame tim-
ing. Note that the short frame timing on the input enables can
only be used with the 32 kbps transcoding rate. The number
of data clock falling edges enclosed by the input enable line
(EIE or DIE) determines both the short frame or long frame
mode and the transcoding rate. The mode of the input or out-
put is determined each frame. In all modes, the data is cap-
tured by the MC145532 on the falling edge of either EDC or
DDC.
ENCODER INPUT — SHORT FRAME
Figure 1 shows the timing of the encoder data clock
(EDC), the encoder input enable (EIE), and the encoder data
input (EDI) pins in short frame operation.
The determination of short frame mode is made by the
MC145532 based on one falling EDC edge while EIE is high.
MOTOROLA
MC145532
3
DECODER OUTPUT — SHORT FRAME
Figure 7 shows the timing of the decoder output in short
frame mode.
The DDO will provide the 8–bit PCM word for the decoding
rate that was selected for this frame of data on the decoder
input pins. The data is loaded into the MC145532 during one
frame, decoded on the next frame, and read during the third
frame.
DECODER OUTPUT — LONG FRAME
Figure 8 shows the timing of the decoder output in long
frame mode. Note that at least eight bits are presented to the
output, provided that at least two falling edges of DDC are
seen while DOE is high. The enable can be used to extend
the LSB to a full DDC period and/or cause the eight bits of
data to be recirculated to the output pin until the enable falls.
STANDARDS INFORMATION
The following standards apply to the MC145532:
T1.301–1987 — 32 kbps ADPCM
T1.303–1988 — 24 kbps ADPCM
CCITT G.721–1988, G.723–1988, and G.726 — 32 kbps
and 24 kbps
CCITT, ITU–T, TIA, and EIA documents may be obtained
by contacting Global Engineering Documents in the USA at
(800) 854–7179, or internationally at (303) 397–7956.
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS)
Rating
DC Supply Voltage
Voltage, Any Pin to VSS
DC Current, Any Pin
Operating Temperature
Storage Temperature
Symbol
VDD
V
Iin
TA
Tstg
Value
– 0.5 to + 7.0
– 0.5 to VDD + 0.5
±
10
– 40 to + 85
– 85 to + 150
Unit
V
V
mA
°C
°C
This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to this high impedance circuit.
For proper operation it is recommended that
Vin and Vout be constrained to the range VSS
≤
(Vin or Vout)
≤
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD).
RECOMMENDED OPERATING CONDITIONS
(TA = – 40 to + 85°C)
Parameter
DC Supply Voltage
Power Dissipation
Symbol
VDD
PD
Min
4.50
—
Max
5.50
0.28
Unit
V
W
DIGITAL CHARACTERISTICS
(VDD = 5.0 V, TA = – 40 to + 85°C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
High Level Output Voltage (IOH = – 2.0 mA)
Low Level Output Voltage (IOL = 2.0 MA)
Output Leakage Current (VDD = 5.5 V)
DDO, EDO
DDO, EDO
DDO, EDO
Mode, DOE, DDC, DDI, DIE, EIE, EDI, EDC, EOE
Mode, DOE, DDC, DDI, DIE, EIE, EDI, EDC, EOE
RESET, APD, SPC
RESET, APD, SPC
Symbol
VIH
VIL
VIH
VIL
Iin
Cin
VOH
VOL
Ilkg
Min
2.0
—
0.7 VDD
—
—
—
4.6
—
—
Max
—
0.8
—
0.3 VDD
±
1.0
10
—
0.4
±
5.0
Unit
V
V
V
V
µA
pF
V
V
µA
SWITCHING CHARACTERISTICS
(VDD = 5.0 V, TA = – 40 to + 85°C)
Parameter
SPC Frequency
SPC Duty Cycle
Min
19.990
45
Max
23
55
Unit
MHz
%
MC145532
4
MOTOROLA
ENCODER INPUT — SHORT FRAME
(VDD = 5.0 V, TA = – 40 to + 85°C)
Parameter
Enable Low Setup Time
Enable Low Hold Time
Enable Valid Time
Enable Hold Time
Data Valid Time
Data Hold Time
Symbol
tsu(EIE)L
th(EIE)H
tV(EIE)
th(EIE)
tv(EDI)
th(EDI)
Min
15
30
15
15
15
15
Max
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
EDC
1
2
3
4
5
6
7
8
EIE
LSB
EDI
MSB
MSB
LSB
EDC
th(EIE)H
EIE
th(EIE)
tv(EIE)
tsu(EIE)L
EDI
tv(EDI)
MSB
th(EDI)
Figure 1. Encoder Input Timing — Short Frame
MOTOROLA
MC145532
5
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