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DG406, DG407
Data Sheet
March 13, 2006
FN3116.9
Single 16-Channel/Differential 8-Channel,
CMOS Analog Multiplexers
The DG406 and DG407 monolithic CMOS analog
multiplexers are drop-in replacements for the popular
DG506A and DG507A series devices. They each include an
array of sixteen analog switches, a TTL and CMOS
compatible digital decode circuit for channel selection, a
voltage reference for logic thresholds, and an ENABLE input
for device selection when several multiplexers are present.
These multiplexers feature lower signal ON resistance
(<100Ω) and faster transition time (t
TRANS
< 300ns)
compared to the DG506A and DG507A. Charge injection
has been reduced, simplifying sample and hold applications.
The improvements in the DG406 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 30V
P-P
signals when operating with
±15V
power
supplies.
The sixteen switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with
analog signals is quite low over a
±5V
analog input range.
Features
• ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . 100Ω
• Low Power Consumption (P
D
) . . . . . . . . . . . . . . . <1.2mW
• Fast Transition Time (Max) . . . . . . . . . . . . . . . . . . . . 300ns
• Low Charge Injection
• TTL, CMOS Compatible
• Single or Split Supply Operation
•
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Battery Operated Systems
• Data Acquisition
• Medical Instrumentation
• Hi-Rel Systems
• Communication Systems
• Automatic Test Equipment
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinouts
DG406 (PDIP, SOIC)
TOP VIEW
V+ 1
NC 2
NC 3
S
16
4
S
15
5
S
14
6
S
13
7
S
12
8
S
11
9
S
10
10
S
9
11
GND 12
NC 13
A
3
14
28 D
27 V-
26 S
8
25 S
7
24 S
6
23 S
5
22 S
4
21 S
3
20 S
2
19 S
1
18 EN
17 A
0
16 A
1
15 A
2
DG407 (PDIP, SOIC)
TOP VIEW
V+ 1
D
B
2
NC 3
S
8B
4
S
7B
5
S
6B
6
S
5B
7
S
4B
8
S
3B
9
S
2B
10
S
1B
11
GND 12
NC 13
NC 14
28 D
A
27 V-
26 S
8A
25 S
7A
24 S
6A
23 S
5A
22 S
4A
21 S
3A
20 S
2A
19 S
1A
18 EN
17 A
0
16 A
1
15 A
2
Ordering Information
PART
NUMBER
DG406DJ
DG406DJZ
(See Note)
DG406DY
DG406DY-T
DG406DYZ
(See Note)
DG406DYZ-T
(See Note)
DG407DJ
DG407DJZ
(Note)
DG407DY
DG407DYZ
(Note)
PART
MARKING
DG406DJ
DG406DJZ
DG406DY
DG406DY
DG406DYZ
DG406DYZ
DG407DJ
DG407DJZ
DG407DY
DG407DYZ
TEMP.
RANGE (°C) PACKAGE
-40 to 85
-40 to 85
-40 to 85
28 Ld PDIP
PKG.
DWG. #
E28.6
28 Ld PDIP* E28.6
(Pb-free)
28 Ld SOIC
M28.3
28 Ld SOIC Tape and Reel M28.3
-40 to 85
28 Ld SOIC
(Pb-free)
M28.3
28 Ld SOIC Tape and Reel M28.3
(Pb-free)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
28 Ld PDIP
E28.6
28 Ld PDIP* E28.6
(Pb-free)
28 Ld SOIC
28 Ld SOIC
(Pb-free)
M28.3
M28.3
*Pb-free PDIPs can be used for through hole wave solder processing only. They are
not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or
1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2003, 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
DG406, DG407
Schematic Diagram
(Typical Channel)
V+
GND
V
REF
D
A
0
V+
A
X
LEVEL
SHIFT
DECODE/
DRIVE
V-
S
1
V+
EN
S
N
V-
Functional Diagrams
DG406
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 16
D
S
1B
S
2B
S
3B
S
4B
S
5B
S
6B
S
7B
S
8B
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ENABLE
ADDRESS DECODER
1 OF 8
D
B
S
1A
S
2A
S
3A
S
4A
S
5A
S
6A
S
7A
S
8A
D
A
DG407
ENABLE
A
0
A
1
A
2
A
3
EN
A
0
A
1
A
2
EN
2
FN3116.9
March 13, 2006
DG406, DG407
DG406 TRUTH TABLE
A
3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A
2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ON SWITCH
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
2
X
0
0
0
0
1
1
1
1
A
1
X
0
0
1
1
0
0
1
1
DG407 TRUTH TABLE
A
0
X
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
ON SWITCH PAIR
None
1
2
3
4
5
6
7
8
Logic “0” = V
AL
< 0.8V.
Logic “1” = V
AH
> 2.4V.
X = Don’t Care.
3
FN3116.9
March 13, 2006
DG406, DG407
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, V
S
, V
D
(Note 1). . . . . . (V-) -2V to (V+) +2V or 20mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 100mA
Thermal Information
Thermal Resistance (Typical, Note1)
θ
JA
(
o
C/W)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(PLCC and SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Signals on S
X
, D
X
, EN or A
X
exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
Electrical Specifications
PARAMETER
DYNAMIC CHARACTERISTICS
Transition Time, t
TRANS
Test Conditions: V+ = +15V, V- = -15V, V
AL
= 0.8V, V
AH
= 2.4V Unless Otherwise Specified
TEST CONDITIONS
TEMP (
o
C)
(NOTE 3)
MIN
(NOTE 4)
TYP
(NOTE 3)
MAX
UNITS
(See Figure 1)
25
Full
-
-
25
10
-
-
-
-
-
-
-
-
200
-
50
-
150
-
70
-
40
-69
7
8
300
400
-
-
200
400
150
300
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
pC
dB
pF
pF
Break-Before-Make Interval, t
OPEN
Enable Turn-ON Time, t
ON(EN)
Enable Turn-OFF Time, t
OFF(EN)
Charge Injection, Q
OFF Isolation, OIRR
Logic Input Capacitance, C
IN
Source OFF Capacitance, C
S(OFF)
Drain OFF Capacitance, C
D(OFF)
DG406
DG407
Drain ON Capacitance, C
D(ON)
DG406
DG407
DIGITAL INPUT CHARACTERISTICS
Logic High Input Voltage, V
INH
Logic Low Input Voltage, V
INL
Logic High Input Current, I
AH
Logic Low Input Current, I
AL
ANALOG SWITCH CHARACTERISTICS
Drain-Source ON Resistance, r
DS(ON)
r
DS(ON)
Matching Between Channels,
∆r
DS(ON)
(See Figure 3)
25
Full
(See Figure 2)
25
Full
25
Full
C
L
= 1nF, V
S
= 0V, R
S
= 0Ω
V
EN
= 0V, R
L
= 1kΩ,
f = 100kHz (Note 7)
f = 1MHz
V
EN
= 0V, V
S
= 0V,
f = 1MHz
V
EN
= 0V, V
D
= 0V,
f = 1MHz
25
25
25
25
25
25
-
-
-
-
160
80
180
90
-
-
-
-
pF
pF
pF
pF
V
EN
= 5V, V
D
= 0V,
f = 1MHz
25
25
Full
Full
V
A
= 2.4V, 15V
V
EN
= 0V, 2.4V, V
A
= 0V
V
D
=
±10V,
I
S
= +10mA (Note 5)
V
D
= 10V, -10V (Note 6)
Full
Full
2.4
-
-1
-1
-
-
-
-
-
0.8
1
1
V
V
µA
µA
Ω
Ω
%
25
Full
25
-
-
-
50
-
5
100
125
-
4
FN3116.9
March 13, 2006
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