DATASHEET
ISL6218
Precision Single-Phase Buck PWM Controller for Intel Mobile Voltage Positioning
IMVP-IV™ and IMVP-IV+™
The ISL6218 Single-Phase Buck PWM control IC, with
integrated half bridge gate driver, provides a precision
voltage regulation system for advanced Pentium-M
microprocessors in notebook computers. This control IC also
features both input voltage feed-forward and average current
mode control for excellent dynamic response, “Loss-less”
current sensing using MOSFET r
DS(ON)
, and user selectable
switching frequencies from 250kHz to 500kHz per phase.
The ISL6218 includes a 6-bit digital-to-analog converter
(DAC) that dynamically adjusts the CORE PWM output
voltage from 0.700V to 1.708V in 16mV steps, and conforms
to the Intel IMVP-IV
mobile VID specification. The ISL6218
also has logic inputs to select Active, Deep Sleep and
Deeper Sleep modes of operation. A precision reference,
remote sensing and proprietary architecture with integrated
processor-mode compensated “Droop” provides excellent
static and dynamic CORE voltage regulation.
Another feature of the ISL6218 IC controller is the internal
PGOOD delay circuit that holds the PGOOD pin low for
3ms to 12ms after the VCCP and VCC_MCH regulators are
within regulation. This PGOOD signal is masked during VID
changes. Output overvoltage and undervoltage are
monitored and result in the converter latching off and
PGOOD signal being held low.
The overvoltage and undervoltage thresholds are 112% and
84% of the VID, Deep or Deeper Sleep setpoint. Overcurrent
protection features a 32 cycle overcurrent shutdown.
PGOOD, Overvoltage, Undervoltage and Overcurrent
provide monitoring and protection for the microprocessor
and power system. The ISL6218 IC is available in a
38 Ld TSSOP and 40 Ld QFN package.
FN9101
Rev 6.00
August 6, 2007
Features
• IMVP-IV
Compliant CORE Regulator
• Single-Phase Power Conversion
• “Loss-less” Current Sensing for Improved Efficiency and
Reduced Board Area
- Optional Discrete Precision Current Sense Resistor
• Internal Gate Drive and Boot-Strap Diode
• Precision CORE Voltage Regulation
- 0.8% System Accuracy Over-temperature
• 6-Bit Microprocessor Voltage Identification Input
• Programmable “Droop” and CORE Voltage Slew Rate to
Comply with IMVP-IV
Specification
• Discontinuous Mode Of Operation for Increased Light
Load Efficiency in Deep and Deeper Sleep Mode
• Direct Interface with System Logic (STP_CPU and
DPRSLPVR) for Deep and Deeper Sleep Modes of
Operation
• Easily Programmable Voltage Setpoints for Initial “Boot”,
Deep Sleep and Deeper Sleep Modes
• Excellent Dynamic Response
- Combined Voltage Feed-Forward and Average Current
Mode Control
• Overvoltage, Undervoltage and Overcurrent Protection
• Power-good Output with Internal Blanking During VID and
Mode Changes
• User Programmable Switching Frequency of 250kHz to
500kHz
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER
ISL6218CV*
ISL6218CVZ* (Note)
ISL6218CVZA* (Note)
ISL6218CRZ* (Note)
PART MARKING
ISL 6218CV
ISL 6218CVZ
ISL 6218CVZ
ISL62 18CRZ
TEMP. RANGE (°C)
-10 to +85
-10 to +85
-10 to +85
-10 to +85
PACKAGE
38 Ld TSSOP
38 Ld TSSOP (Pb-free)
38 Ld TSSOP (Pb-free)
40 Ld 6x6 QFN (Pb-free)
PKG. DWG #
M38.173
M38.173
M38.173
L40.6x6
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN9101 Rev 6.00
August 6, 2007
Page 1 of 19
ISL6218
Pinouts
ISL6218
(38 LD TSSOP)
TOP VIEW
VDD
DACOUT
DSV
FSET
NC
EN
DRSEN
DSEN
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
EA+
COMP
FB
SOFT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ISL6218
38 VBAT
37 ISEN
36 PHASE
35 UG
34 BOOT
33 VSSP
32 LG1
31 VDDP
30 NC
29 NC
28 NC
27 NC
26 NC
25 NC
24 VSEN
23 DRSV
22 STV
21 OCSET
20 VSS
ISL6218
(40 LD QFN)
TOP VIEW
DACOUT
PHASE
BOOT
31
30 VSSP
29 LG
28 VDDP
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
11
EA+
12
COMP
13
FB
14
NC
15
SOFT
16
VSS
17
OCSET
18
STV
19
DRSV
20
VSEN
VBAT
FSET
ISEN
VDD
DSV
40
EN
DRSEN
DSEN
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
1
2
3
4
5
6
7
8
9
10
39
38
37
36
35
34
33
FN9101 Rev 6.00
August 6, 2007
UG
32
NC
Page 2 of 19
ISL6218
Absolute Maximum Ratings
Supply Voltage VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25V
Boot1 and UGATE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+33V
Phase1 and ISEN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V
Boot1 with respect to Phase1 . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
UGATE1. . . . . . . . . . . . . . . . . . . . (Phase1 - 0.3V) to (Boot1 + 0.3V)
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
TSSOP Package (Note 1) . . . . . . . . . . . .
72
N/A
QFN Package (Notes 2, 3) . . . . . . . . . . .
32
4.5
Maximum Operating Junction Temperature. . . . . . . . . . . . . . +125°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to 21V
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
3. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
4. Limits established by characterization and are not production tested.
Electrical Specifications
PARAMETER
INPUT SUPPLY POWER
Input Supply Current, I(VDD)
Operating Conditions: V
DD
= 5V, T
A
= -10°C to +85°C, Unless Otherwise Specified.
TEST CONDITIONS
MIN
TYP
MAX
UNITS
EN = 3.3V, DSEN = 0, DRSEN = 0
EN = 0V
-
-
4.39
4.10
1.4
1
4.45
4.20
-
-
4.5
4.37
mA
µA
V
V
POR (Power-On Reset) Threshold
VDD Rising
VDD Falling
REFERENCE AND DAC
System Accuracy
DAC (VID0 to VID5) Input Low
Voltage
DAC (VID0 to VID5) Input High
Voltage
Maximum Output Voltage
Minimum Output Voltage
CHANNEL GENERATOR
Frequency, f
SW
Adjustment Range
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
C
L
= 20pF
C
L
= 20pF
-
-
-
100
18
4.0
-
-
-
dB
MHz
V/µs
R
Fset
= 243k, ±1%
225
250
250
-
275
500
kHz
kHz
Percent system deviation from programmed VID Codes @ 1.356
DAC Programming Input Low Threshold Voltage
DAC Programming Input High Threshold Voltage
-0.8
-
0.7
-
-
-
-
-
1.708
0.70
0.8
0.3
-
-
-
%
V
V
V
V
FN9101 Rev 6.00
August 6, 2007
Page 3 of 19
ISL6218
Electrical Specifications
PARAMETER
ISEN
Full Scale Input Current
Overcurrent Threshold
Soft-Start Current
Droop Current
GATE DRIVER
UGATE Source Resistance
UGATE Source Current (Note 4)
UGATE Sink Resistance
UGATE Sink Current (Note 4)
LGATE Source Resistance
LGATE Source Current (Note 4)
LGATE Sink Resistance
LGATE Sink Current (Note 4)
BOOTSTRAP DIODE
Forward Voltage
POWER GOOD MONITOR
PGOOD Sense Current
PGOOD Pull-Down MOSFET r
DS(ON)
Undervoltage Threshold
(VSEN/VREF)
Undervoltage Threshold
(VSEN/VREF)
PGOOD Low Output Voltage
LOGIC THRESHOLD
EN, DSEN, DRSEN Low
EN, DSEN, DRSEN High
PROTECTION
Overvoltage Threshold (V
SEN
/V
REF
)
DELAY TIME
Delay Time from LGATE Falling to
UGATE Rising
Delay Time from UGATE Falling to
LGATE Rising
VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 1V,
LGATE = 1V
VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 1V,
LGATE = 1V
10
10
18
18
30
30
ns
ns
V
SEN
Rising
-
112.0
-
%
-
2
-
-
1
-
V
V
VSEN Rising
VSEN Falling
I
PGOOD
= 4mA
Operating Conditions: V
DD
= 5V, T
A
= -10°C to +85°C, Unless Otherwise Specified.
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
ROCSET = 110k (see Figure 10)
SOFT = 0V
ISEN = 32µA
-
-
12.0
32
54
31
14
-
-
-
16.0
µA
µA
µA
µA
500mA Source Current
V
UGATE-PHASE
= 2.5V
-
-
-
-
-
-
-
-
1
2
1
2
1
2
0.5
4
1.5
-
1.5
-
1.5
-
0.8
-
A
A
A
A
500mA Sink Current
V
UGATE-PHASE
= 2.5V
500mA Source Current
V
LGATE
= 2.5V
500mA Sink Current
V
LGATE
= 2.5V
VDDP = 5V, Forward Bias Current = 10mA
0.57
0.68
0.74
V
2.43
56
-
-
-
-
63
85.0
84.0
0.26
-
82
-
-
0.4
mA
%
%
V
FN9101 Rev 6.00
August 6, 2007
Page 4 of 19
ISL6218
Functional Pin Description 38 Ld TSSOP
VDD
DACOUT
DSV
FSET
NC
EN
DRSEN
DSEN
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
EA+
COMP
FB
SOFT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ISL6218
38 VBAT
37 ISEN
36 PHASE
35 UG
34 BOOT
33 VSSP
32 LG
31 VDDP
30 NC
29 NC
28 NC
27 NC
26 NC
25 NC
24 VSEN
23 DRSV
22 STV
21 OCSET
20 VSS
VSEN
This pin is used for remote sensing of the microprocessor
CORE voltage.
COMP
This pin provides connection to the error amplifier output.
FB
This pin is connected to the inverting input of the error
amplifier.
EA+
This pin is connected to the non-inverting input of the error
amplifier and is used for setting the “Droop” voltage.
STV
The voltage on this pin sets the initial start-up or “Boot” voltage.
SOFT
This pin programs the slew rate of VID changes, Deep Sleep
and Deeper Sleep transitions, and soft-start after initializing.
This pin is connected to ground via a capacitor, and to EA+
through an external “Droop” resistor.
VDD
This pin is used to connect +5V to the IC to supply all power
necessary to operate the chip. The IC starts to operate when
the voltage on this pin exceeds the rising POR threshold and
shuts down when the voltage on this pin drops below the falling
POR threshold.
DSEN
This pin connects to system logic “STP_CPU” and enables
Deep Sleep mode of operation. Deep Sleep is enabled when a
logic LOW signal is detected on this pin.
DRSEN
This pin connects to system logic “DPRSLPVR” and enables
Deeper Sleep mode of operation when a logic HIGH is
detected on this pin.
VDDP
This pin provides a low ESR bypass connection to the internal
gate drivers for the +5V source.
VBAT
Voltage on this pin provides feed-forward battery information
that adjusts the oscillator ramp amplitude.
PGOOD
This pin is used as an input and an output and is tied to the
Vccp and Vcc_mch PGOOD signals. During start-up, this pin is
recognized as an input, and prevents further slewing of the
output voltage from the “Boot” level until PGOOD from Vccp
and Vcc_mch is enabled High. After start-up, this pin has an
open drain output used to indicate the status of the CORE
output voltage. This pin is pulled low when the system output is
outside of the regulation limits. PGOOD includes a timer for
power-on delay.
FSET
A resistor from this pin to ground programs the switching
frequency.
ISEN
This pin is used as current sense input from the converter
channel phase node.
DACOUT
This pin provides access to the output of the Digital-to-Analog
Converter.
EN
This pin is connected to the system signal VR_ON and
provides the enable/disable function for the PWM controller.
DSV
The voltage on this pin provides the setpoint for output voltage
during Deep Sleep Mode of operation.
OCSET
A resistor from this pin to ground sets the overcurrent
protection threshold. The current from this pin should be
between 10µA and 25µA (70k to 175k equivalent pull-down
resistance).
DRSV
The voltage on this pin provides the setpoint for output voltage
during Deeper Sleep Mode of operation.
FN9101 Rev 6.00
August 6, 2007
Page 5 of 19
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