MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Serial Input PLL Frequency
Synthesizer
The MC12206 is a 2.0GHz Bipolar monolithic serial input phase locked
loop (PLL) synthesizer with pulse–swallow function. It is designed to
provide the high frequency local oscillator signal of an RF transceiver in
handheld communication applications.
Motorola’s advanced Bipolar MOSAIC™ V technology is utilized for
low power operation at a minimum supply voltage of 2.7V. The device is
designed for operation over 2.7 to 5.5V supply range for input frequencies
up to 2.0GHz with a typical current drain of 7.4mA. The low power
consumption makes the MC12206 ideal for handheld battery operated
applications such as cellular or cordless telephones, wireless LAN or
personal communication services. A dual modulus prescaler is integrated
to provide either a 64/65 or 128/129 divide ratio.
For additional applications information, two
InterActiveApNote
™
documents containing software (based on a Microsoft Excel
spreadsheet) and an Application Note are available. Please order
DK305/D and DK306/D from the Motorola Literature Distribution Center.
MC12206
MECL PLL COMPONENTS
Serial Input PLL
Frequency Synthesizer
16
•
Low Power Supply Current of 6.7mA Typical for ICC and 0.7mA Typical
for IP
1
•
Supply Voltage of 2.7 to 5.5V
•
Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or
128/129
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
•
On–Chip Reference Oscillator/Buffer
•
Programmable Reference Divider Consisting of a Binary 14–Bit
Programmable Reference Counter
20
1
•
Programmable Divider Consisting of a Binary 7–Bit Swallow Counter
and an 11–Bit Programmable Counter
•
Phase/Frequency Detector With Phase Conversion Function
•
Balanced Charge Pump Outputs
•
Dual Internal Charge Pumps for Bypassing the First Stage of the Loop
Filter to Decrease Lock Time
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–03
•
Outputs for External Charge Pump
•
Operating Temperature Range of –40°C to +85°C
•
Space Efficient Plastic Surface Mount SOIC or TSSOP Packages
MAXIMUM RATINGS*
Symbol
VCC
VP
Tstg
Parameter
Power Supply Voltage, Pin 4 (Pin 5 in 20–lead package)
Power Supply Voltage, Pin 3 (Pin 4 in 20–lead package)
Storage Temperature Range
Value
–0.5 to +6.0
VCC to +6.0
–65 to +150
Unit
VDC
VDC
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
MOSAIC V, Mfax and
InterActiveApNote
are trademarks of Motorola, Inc.
1/97
©
Motorola, Inc. 1997
1
REV 3
MC12206
φR
16
φP
15
fOUT BISW
14
13
FC
12
LE
11
DATA
10
CLK
9
Pinout: 16–Lead Package
(Top View)
1
2
3
4
VCC
5
Do
FC
15
6
GND
LE
14
7
LD
DATA
13
8
fIN
NC
12
CLK
11
OSCin OSCout VP
φR
20
NC
19
φP
18
fOUT BISW
17
16
Pinout: 20–Lead Package
(Top View)
1
OSCin
2
3
4
VP
5
VCC
6
Do
7
GND
8
LD
9
NC
10
fIN
NC OSCout
PIN NAMES
Pin
OSCin
OSCout
VP
VCC
Do
GND
LD
fIN
CLK
DATA
LE
I/O
I
O
—
—
O
—
O
I
I
I
I
Function
Oscillator input. A crystal is connected between OSCin and OSCout. An external
source can be AC coupled into this input
Oscillator output. Pin should be left open if external source is used
Power supply for charge pumps (VP should be greater than or equal to VCC) VP
provides power to the Do, BISW and
φP
outputs
Power supply voltage input. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
Internal charge pump output. Do remains on at all times
Ground
Lock detect, phase comparator output
Prescaler input. The VCO signal is AC–coupled into this pin
Clock input. Rising edge of the clock shifts data into the shift registers
Binary serial data input
Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data
stored in the shift register is transferred into the appropriate latch (depending on
the level of control bit). Also, when LE is HIGH or OPEN, the output of the second
internal charge pump is connected to the BISW pin
Phase control select (with internal pull up resistor). When FC is LOW, the
characteristics of the phase comparator and charge pump are reversed. FC also
selects fp or fr on the fOUT pin
Analog switch output. When LE is HIGH or OPEN (“analog switch is ON”) the
output of the second charge pump is connected to the BISW pin. When LE is LOW,
BISW is high impedance
Phase comparator input signal. When FC is HIGH, fOUT=fr, programmable
reference divider output; when FC is LOW, fOUT=fp, programmable divider output
Output for external charge pump. Standard CMOS output level
Output for external charge pump. Standard CMOS output level
No connect
16–Lead Pkg
Pin No.
1
2
3
4
5
6
7
8
9
10
11
20–Lead Pkg
Pin No.
1
3
4
5
6
7
8
10
11
13
14
FC
I
12
15
BISW
O
13
16
fOUT
φP
φR
NC
O
O
O
—
14
15
16
—
17
18
20
2, 9, 12, 19
MOTOROLA
2
HIPERCOMM
BR1334 — Rev 4
MC12206
15–BIT SHIFT REGISTER
15
15–BIT LATCH
14
1
PROGRAMMABLE REFERENCE DIVIDER
OSCin
OSCout
CRYSTAL
OSCILLATOR
14–BIT REFERENCE COUNTER
fr
PHASE/FREQUENCY
DETECTOR
CHARGE
PUMP 1
LE
LE
DATA
7
CLK
7–BIT
LATCH
7
CONTROL
BIT
DATA
18–BIT SHIFT REGISTER
11
DIVIDER
OUTPUT MUX
fOUT
LD
φP
φR
FC
Do
CHARGE
PUMP 2
BISW
11–BIT LATCH
11
fIN
PRESCALER
64/65 or 128/129
PROGRAMMABLE DIVIDER
7–BIT
SWALLOW
A–COUNTER
11–BIT
PROGRAMMABLE
N–COUNTER
fp
CONTROL LOGIC
Figure 1. MC12206 Block Diagram
HIPERCOMM
BR1334 — Rev 4
3
MOTOROLA
MC12206
DATA ENTRY FORMAT
The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit
programmable reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock
shifts one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred
into the latch when load enable pin is HIGH or OPEN.
Control bit:
“H” = data is transferred into 15–bit latch of programmable reference divider
“L” = data is transferred into 18–bit latch of programmable divider
WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will
affect the VCO.
PROGRAMMABLE REFERENCE DIVIDER
16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If
the control bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to
16383) and the prescaler divide ratio (SW=0 for
÷128/129,
SW=1 for
÷64/65).
An R divide ratio less than 8 is prohibited.
For Control bit (C) = HIGH:
SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)
MSB
CONTROL BIT (LAST BIT)
LSB
S
W
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
C
SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE
REFERENCE COUNTER (R–COUNTER)
DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER
Divide
Ratio R
8
9
•
16383
R
14
0
0
•
1
R
13
0
0
•
1
R
12
0
0
•
1
R
11
0
0
•
1
R
10
0
0
•
1
R
9
0
0
•
1
R
8
0
0
•
1
R
7
0
0
•
1
R
6
0
0
•
1
R
5
0
0
•
1
R
4
1
1
•
1
R
3
0
0
•
1
R
2
0
0
•
1
R
1
0
1
•
1
PRESCALER SELECT BIT
Prescaler Divide Ratio P
128/129
64/65
SW
0
1
MOTOROLA
4
HIPERCOMM
BR1334 — Rev 4
MC12206
PROGRAMMABLE DIVIDER
19–bit serial data format for the programmable divider is shown below. If the control bit is LOW, data is transferred from the 18–bit
shift register into the 18–bit latch which specifies the swallow A–counter divide ratio (0 to 127) and the programmable N–counter
divide ratio (16 to 2047). An N–counter divide ratio less than 16 is prohibited.
For Control bit (C) = LOW:
MSB (FIRST BIT)
CONTROL BIT (LAST BIT)
LSB
N
18
N
17
N
16
N
15
N
14
N
13
N
12
N
11
N
10
N
9
N
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
C
SETTING BITS FOR
DIVIDE RATIO OF
PROGRAMMABLE N–COUNTER
SETTING BITS FOR
DIVIDE RATIO OF
SWALLOW A–COUNTER
DIVIDE RATIO OF PROGRAMMABLE N–COUNTER
Divide
Ratio N
16
17
•
2047
N
18
0
0
•
1
N
17
0
0
•
1
N
16
0
0
•
1
N
15
0
0
•
1
N
14
0
0
•
1
N
13
0
0
•
1
N
12
1
1
•
1
N
11
0
0
•
1
N
10
0
0
•
1
N
9
0
0
•
1
N
8
0
1
•
1
DIVIDE RATIO OF SWALLOW A–COUNTER
Divide
Ratio A
0
1
•
127
A
7
0
0
•
1
A
6
0
0
•
1
A
5
0
0
•
1
A
4
0
0
•
1
A
3
0
0
•
1
A
2
0
0
•
1
A
1
0
1
•
1
DIVIDE RATIO SETTING
fvco = [(P•N)+A]•fosc
÷
R with A<N
fvco: Output frequency of external voltage controlled oscillator (VCO)
N:
Preset divide ratio of binary 11–bit programmable counter (16 to 2047)
A:
Preset divide ratio of binary 7–bit swallow counter (0 to 127, A<N)
fosc: Output frequency of the external frequency oscillator
R:
Preset divide ratio of binary 14–bit programmable reference counter (8 to 16383)
P:
Preset mode of dual modulus prescaler (64 or 128)
DATA
N18:MSB
(SW:MSB)
N17
(R14)
N8
(R7)
A7
(R6)
A1
(R1)
C = CONTROL BIT (LAST BIT)
(C = CONTROL BIT (LAST BIT))
CLK
LE
ts(C→LE)
ts(D)
th(D)
tCW
tEW
NOTES:Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK.
ts(D) = Setup Time DATA to CLK
ts(D)
≥
10ns
th(D) = Hold Time DATA to CLK
th(D)
≥
20ns
tCW = CLK Pulse Width
tCW
≥
30ns
tEW = LE Pulse Width
tEW
≥
20ns
ts(C→LE) = Setup Time CLK to LE
ts(C→LE)
≥
30ns
Figure 2. Serial Data Input Timing
HIPERCOMM
BR1334 — Rev 4
5
MOTOROLA
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