PRELIMINARY TECHNICAL DATA
Preliminary Technical Data
FEATURES
225 ps Propagation Delay through the Switch
4.5 Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Small Signal Bandwidth 610 MHz
Level Translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
24-Lead TSSOP and LFCSP Packages
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Signal Switching
2.5 V/3.3 V, 10-Bit, 2-Port
Level Translating, Bus Switch
ADG3246
FUNCTIONAL BLOCK DIAGRAM
A0
B0
A9
B9
BE
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3246 is a 2.5 V or 3.3 V, 10-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.
The switches are enabled by means of the Bus Enable (BE)
input signal. These digital switches allow bidirectional signals to
be switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs occurs. Similarly, if the device is operated
from a 2.5 V supply and 2.5 V inputs are applied, the device will
translate the outputs to 1.8 V. In addition to this, the ADG3246
has a level translating select pin (SEL) . When
SEL
is low, V
CC
is
reduced internally, allowing for level translation between 3.3 V
inputs and 1.8 V outputs. This makes the device suited to appli-
cations requiring level translation between different supplies, such
as converter to DSP/microcontroller interfacing.
1.
2.
3.
4.
5.
3.3 V or 2.5 V supply operation
Extremely low propagation delay through switch
4.5
Ω
switches connect inputs to outputs
Level/voltage translation
24-lead 4 mm
×
4 mm LFCSP and 24-lead TSSOP packages
REV. PrC
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
PRELIMINARY TECHNICAL DATA
ADG3246–SPECIFICATIONS
Parameter
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Leakage Current
OFF State Leakage Current
ON State Leakage Current
Max Pass Voltage
1
(V
CC
= 2.3 V to 3.6 V, GND = 0 V, all specifications T
MIN
to T
MAX
, unless
otherwise noted.)
B Version
Typ
2
Symbol
V
INH
V
INH
V
INL
V
INL
I
I
I
OZ
V
P
Conditions
V
CC
= 2.7 V to 3.6 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 2.3 V to 2.7 V
0
≤
A, B
≤
V
CC
0
≤
A, B
≤
V
CC
V
A
/V
B
= V
CC
=
SEL
= 3.3 V, I
O
= –5
µA
V
A
/V
B
= V
CC
=
SEL
= 2.5 V, I
O
= –5
µA
V
A
/V
B
= V
CC
= 3.3 V,
SEL
= 0 V, I
O
= –5
µA
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
C
L
= 50 pF, V
CC
=
SEL
= 3 V
V
CC
= 3.0 V to 3.6 V;
SEL
= V
CC
V
CC
= 3.0 V to 3.6 V;
SEL
= V
CC
V
CC
= 3.0 V to 3.6 V;
SEL
= 0 V
V
CC
= 3.0 V tp 3.6 V;
SEL
= 0 V
V
CC
= 2.3 V to 2.7 V;
SEL
= V
CC
V
CC
= 2.3 V to 2.7 V;
SEL
= V
CC
V
CC
=
SEL
= 3.3 V; V
A
/V
B
= 2 V
V
CC
=
SEL
= 3.3 V; V
A
/V
B
= 2 V
Min
2.0
1.7
Max
Unit
V
V
V
V
µA
µA
µA
V
V
V
pF
pF
pF
pF
2.0
1.5
1.5
±
0.01
±
0.01
±
0.01
2.5
1.8
1.8
5
5
10
6
0.8
0.7
±
1
±
1
±
1
2.9
2.1
2.1
CAPACITANCE
3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS
3
Propagation Delay A to B or B to A, t
PD4
Propagation Delay Matching
5
Bus Enable Time
BE
to A or B
6
Bus Disable Time
BE
to A or B
6
Bus Enable Time
BE
to A or B
6
Bus Disable Time
BE
to A or B
6
Bus Enable Time
BE
to A or B
6
Bus Disable Time
BE
to A or B
6
Max Data Rate
Channel Jitter
Operating Frequency—Bus Enable
DIGITAL SWITCH
On Resistance
C
A
OFF
C
B
OFF
C
A
, C
B
ON
C
IN
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
PZH
, t
PZL
t
PHZ
, t
PLZ
1
1
0.5
0.5
0.5
0.5
3.2
3.2
2.2
1.7
2.2
1.75
1.244
50
0.225
22.5
4.8
4.8
3.3
2.9
3
2.6
f
BE
R
ON
V
CC
= 3 V,
SEL
= V
CC
, V
A
= 0 V, I
BA
= 8 mA
V
CC
= 3 V,
SEL
= V
CC
, V
A
= 1.7 V, I
BA
= 8 mA
V
CC
= 2.3 V,
SEL
= V
CC
, V
A
= 0 V, I
BA
= 8 mA
V
CC
= 2.3 V,
SEL
= V
CC
, V
A
= 1 V, I
BA
= 8 mA
V
CC
= 3 V,
SEL
= 0 V, V
A
= 0 V, I
BA
= 8 mA
V
CC
= 3 V,
SEL
= 0 V, V
A
= 1 V, I
BA
= 8 mA
V
CC
= 3 V,
SEL
= V
CC
, V
A
= 0 V, I
BA
= 8 mA
V
CC
= 3 V,
SEL
= V
CC
, V
A
= 1 V, I
BA
= 8 mA
2.3
I
CC
I
CC
I
CC
Digital Inputs = 0 V or V
CC
;
SEL
= V
CC
Digital Inputs = 0 V or V
CC
;
SEL
= 0 V
V
CC
= 3.6 V,
BE
= 3.0 V;
SEL
= V
CC
0.001
0.65
4.5
15
5
11
5
14
0.45
0.65
10
8
28
9
18
8
ns
ps
ns
ns
ns
ns
ns
ns
Gbps
ps p-p
MHz
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
V
µA
mA
µA
On Resistance Matching
POWER REQUIREMENTS
V
CC
Quiescent Power Supply Current
Increase in I
CC
per Input
7
R
ON
3.6
1
1.2
130
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Typical values are at 25°C unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical R
ON
of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6
See Timing Measurement Information.
7
This current applies to the control pin (BE) only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
–2–
REV. PrC
PRELIMINARY TECHNICAL DATA
ADG3246
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C, unless otherwise noted.)
V
CC
to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
LFCSP Package
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 35°C/W
TSSOP Package
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one absolute maximum
rating may be applied at any one time.
ORDERING GUIDE
Model
ADG3246BCP
ADG3246BRU
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Chip Scale Package (LFCSP)
Thin Shrink Small Outline Package (TSSOP)
Package Option
CP-24
RU-24
Table I. Pin Description
Table II. Truth Table
Pin Mnemonic
BE
SEL
Ax
Bx
Description
Bus Enable (Active Low)
Level Translation Select
Port A, Inputs or Outputs
Port B, Inputs or Outputs
BE
L
L
H
SEL*
L
H
X
Function
A = B, 3.3 V to 1.8 V Level Shifting
A = B, 3.3 V to 2.5 V/2.5V to 1.8 V Level Shifting
Disconnect
*SEL
= 0 only when V
DD
= 3.3 V
±
10%
PIN CONFIGURATION
24-Lead LFCSP and 24-Lead TSSOP
24 A4
23 A3
22 A2
21 A1
20 A0
19 V
CC
SEL
1
24
23
22
21
V
CC
BE
B0
B1
B2
A0
2
18
BE
17 B0
16 B1
15 B2
14 B3
13 B4
SEL
1
A5 2
A6 3
A7 4
A8 5
A9 6
PIN 1
INDICATOR
A1
3
A2
4
A3
5
ADG3246
TOP VIEW
ADG3246
20
19
A4
6
B3
TOP VIEW
A5
7
(Not to Scale)
18
B4
17
16
15
14
13
GND 7
B9 8
B8 9
B7 10
B6 11
B5 12
A6
8
A7
9
A8
10
B5
B6
B7
B8
B9
A9
11
GND
12
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3246 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. PrC
–3–
PRELIMINARY TECHNICAL DATA
ADG3246
TERMINOLOGY
V
CC
GND
V
INH
V
INL
I
I
I
OZ
I
OL
V
P
R
ON
R
ON
C
X
OFF
C
X
ON
C
IN
I
CC
I
CC
t
PLH
, t
PHL
t
PZH
, t
PZL
t
PHZ
, t
PLZ
Positive Power Supply Voltage
Ground (0 V) Reference
Minimum Input Voltage for Logic 1
Maximum Input Voltage for Logic 0
Input Leakage Current at the Control Inputs
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Max Pass Voltage. The max pass voltage relates to the clipped output voltage of an NMOS device when the switch
input voltage is equal to the supply voltage.
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
On Resistance Match between Any Two Channels, i.e., R
ON
Max - R
ON
Min
OFF Switch Capacitance
ON Switch Capacitance
Control Input Capacitance. This consists of
BE
and
SEL.
Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and
the switches are OFF.
Extra Power Supply Current Component for the
BE
Control Input when the Input is not Driven at the Supplies
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
R
ON
×
C
L
, where C
L
is the load capacitance.
Bus Enable Times. These are times taken to cross the V
T
voltage at the switch output when the switch turns on in
response to the control signal,
BE.
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the con-
trol signal. It is measured as the time taken for the output voltage to change by V from the original quiescent level,
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Maximum Rate at which Data Can Be Passed through the Switch
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel
Operating Frequency of Bus Enable. This is the maximum frequency at which Bus Enable (BE) can be toggled.
Max Data Rate
Channel Jitter
f
BEx
–4–
REV. PrC
PRELIMINARY TECHNICAL DATA
Typical Performance Characteristics–ADG3246
40
35
30
25
T
A
= 25 C
SEL
= V
CC
V
CC
= 3V
40
35
30
25
T
A
= 25 C
SEL
= V
CC
V
CC
= 2.3V
40
35
30
25
V
CC
= 2.5V
20
15
V
CC
= 2.7V
10
5
0
V
CC
= 3.6V
10
5
0
0.5
1.0
2.0
1.5
V
A
/V
B
– V
2.5
3.0
3.5
0
0
0.5
1.0
2.0
1.5
V
A
/V
B
– V
2.5
3.0
10
5
0
T
A
= 25 C
SEL
= 0V
V
CC
= 3V
R
ON
–
R
ON
–
V
CC
= 3.3V
20
15
R
ON
–
V
CC
= 3.3V
20
15
V
CC
= 3.6V
0
0.5
1.0
1.5
2.0
V
A
/V
B
– V
2.5
3.0
3.5
TPC 1. On Resistance vs.
Input Voltage
TPC 2. On Resistance vs.
Input Voltage
TPC 3. On Resistance vs.
Input Voltage
20
V
CC
= 3.3V
SEL
= V
CC
15
15
V
CC
= 2.5V
SEL
= V
CC
3.0
2.5
T
A
= 25 C
SEL
= V
CC
I
O
= –5 A
V
CC
= 3.6V
R
ON
–
85 C
V
OUT
– V
10
2.0
1.5
V
CC
= 3.3V
V
CC
= 3V
R
ON
–
10
85 C
5
5
1.0
40 C
25 C
25 C
40 C
0.5
0
0
0.5
1.0
V
A
/V
B
– V
1.5
2.0
0
0
0
0.5
V
A
/V
B
– V
1.0
1.2
0
0.5
1.0
2.0
1.5
V
CC
– V
2.5
3.0
3.5
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
TPC 5. On Resistance vs. Input
Voltage for Different Temperatures
TPC 6. Pass Voltage vs. V
CC
2.5
T
A
= 25 C
SEL
= V
CC
I
O
= –5 A
V
CC
= 2.7V
2.5
T
A
= 25 C
SEL
= 0V
I
O
= –5 A
V
CC
= 3.6V
1800
1600
1400
1200
V
CC
= 3.3V,
SEL
= 0V
T
A
= 25 C
2.0
2.0
V
OUT
– V
V
CC
= 2.5V
V
CC
= 2.3V
V
CC
= 3.3V
1.0
V
CC
= 3V
I
CC
– A
1.5
V
OUT
– V
1.5
1000
800
600
1.0
0.5
0.5
400
200
V
CC
=
SEL
= 3.3V
V
CC
=
SEL
= 2.5V
0
2
4
6
8 10 12 14 16 18 20
ENABLE FREQUENCY – MHz
0
0
0.5
1.0
1.5
2.0
V
CC
– V
2.5
3.0
0
0
0.5
1.0
1.5
2.0
V
CC
– V
2.5
3.0
3.5
0
TPC 7. Pass Voltage vs. V
CC
TPC 8. Pass Voltage vs. V
CC
TPC 9. I
CC
vs. Enable Frequency
REV. PrC
–5–
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