W83877ATG datasheet, PDF - EEWORLD Datasheet

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W83877ATG: DescriptionMultifunction Peripheral, CMOS, PQFP100, QFP-100; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，194 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw; Environmental Compliance

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W83877ATG Overview

Multifunction Peripheral, CMOS, PQFP100, QFP-100

W83877ATG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Winbond Electronics Corporation
Parts packaging code	QFP
package instruction	QFP, QFP100,.75X.99
Contacts	100
Reach Compliance Code	unknown
Address bus width	16
boundary scan	NO
Bus compatibility	PCI; ISA; IBM PC-AT; PS/2
maximum clock frequency	48 MHz
External data bus width	8
JESD-30 code	R-PQFP-G100
length	20 mm
Number of I/O lines	10
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.75X.99
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	245
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.3 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm
Base Number Matches	1

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W83877ATF

W83877ATG

WINBOND I/O

W83877ATF/W83877ATG

Table of Contents-

1. GENERAL DESCRIPTION ................................................................................................................ 1

2. FEATURES ........................................................................................................................................ 2

3. PIN CONFIGURATION...................................................................................................................... 4

4. PIN DESCRIPTION ........................................................................................................................... 5

4.1

4.2

4.3

4.4

5.1

Host Interface............................................................................................................................ 5

Serial Port Interface .................................................................................................................. 7

Multi-Mode Parallel Port............................................................................................................ 9

FDC Interface.......................................................................................................................... 13

W83877ATF/ATG FDC ........................................................................................................... 15

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.1.8

5.1.9

AT interface ..............................................................................................................................15

FIFO (Data) ..............................................................................................................................15

Data Separator .........................................................................................................................16

Write Precompensation ............................................................................................................16

Perpendicular Recording Mode ................................................................................................16

Tape Drive................................................................................................................................17

FDC Core .................................................................................................................................17

FDC Commands.......................................................................................................................17

FDC Instruction Sets ................................................................................................................18

Status Register A (SA Register) (Read base address + 0).......................................................26

Status Register B (SB Register) (Read base address + 1).......................................................28

Digital Output Register (DO Register) (Write base address + 2) ..............................................30

Tape Drive Register (TD Register) (Read base address + 3)...................................................30

Main Status Register (MS Register) (Read base address + 4).................................................31

Data Rate Register (DR Register) (Write base address + 4) ....................................................31

FIFO Register (R/W base address + 5) ....................................................................................33

Digital Input Register (DI Register) (Read base address + 7)...................................................35

Configuration Control Register (CC Register) (Write base address + 7) ..................................36

5. FDC FUNCTIONAL DESCRIPTION................................................................................................ 15

5.2

Register Descriptions.............................................................................................................. 26

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.2.8

5.2.9

6. UART PORT .................................................................................................................................... 37

6.1

6.2

Universal Asynchronous Receiver/Transmitter (UART A, UART B) ...................................... 37

Register Address .................................................................................................................... 38

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

UART Control Register (UCR) (Read/Write) ............................................................................39

UART Status Register (USR) (Read/Write) ..............................................................................40

Handshake Control Register (HCR) (Read/Write) ....................................................................41

Handshake Status Register (HSR) (Read/Write)......................................................................42

UART FIFO Control Register (UFR) (Write only)......................................................................43

- II -

W83877ATF/W83877ATG

6.2.6

6.2.7

6.2.8

6.2.9

Interrupt Status Register (ISR) (Read only) ..............................................................................44

Interrupt Control Register (ICR) (Read/Write) ..........................................................................45

Programmable Baud Generator (BLL/BHL) (Read/Write).........................................................45

User-defined Register (UDR) (Read/Write) ..............................................................................46

Advanced UART B Register Description ..................................................................................47

Set0-Legacy/Advanced UART Control and Status Registers ...................................................48

Set1 - Legacy Baud Rate Divisor Register ...............................................................................57

Set2 - Interrupt Status

UART FIFO Control Register (ISR/UFR)..........................................58

Set3 - Version ID

and

Mapped Control Registers.....................................................................61

Set4 - TX/RX/Timer counter registers

and

IR control registers.................................................62

Set 5 - Flow control

and

IR control

and

Frame Status FIFO registers ......................................64

Set6 - IR Physical Layer Control Registers...............................................................................68

Set7 - Remote control

and

IR module selection registers.........................................................72

6.3

IR Port ..................................................................................................................................... 47

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

6.3.9

7. PARALLEL PORT ............................................................................................................................ 80

7.1

7.2

Printer Interface Logic............................................................................................................. 80

Enhanced Parallel Port (EPP) ................................................................................................ 82

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

Data Swapper...........................................................................................................................82

Printer Status Buffer .................................................................................................................82

Printer Control Latch and Printer Control Swapper...................................................................83

EPP Address Port ....................................................................................................................84

EPP Data Port 0-3 ....................................................................................................................84

Bit Map of Parallel Port and EPP Registers..............................................................................85

EPP Pin Descriptions ...............................................................................................................85

EPP Operation .........................................................................................................................86

ECP Register and Mode Definitions .........................................................................................87

Data and ecpAFifo Port ............................................................................................................87

Device Status Register (DSR) ..................................................................................................88

Device Control Register (DCR).................................................................................................89

cFifo (Parallel Port Data FIFO) Mode = 010 .............................................................................89

ecpDFifo (ECP Data FIFO) Mode = 011...................................................................................89

tFifo (Test FIFO Mode) Mode = 110 .........................................................................................90

cnfgA (Configuration Register A) Mode = 111 ..........................................................................90

cnfgB (Configuration Register B) Mode = 111 ..........................................................................90

ecr (Extended Control Register) Mode = all..............................................................................91

Bit Map of ECP Port Registers .................................................................................................92

ECP Pin Descriptions ...............................................................................................................93

ECP Operation .........................................................................................................................94

FIFO Operation ........................................................................................................................94

7.3

Extended Capabilities Parallel (ECP) Port ............................................................................. 86

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.3.7

7.3.8

7.3.9

7.3.10

7.3.11

7.3.12

7.3.13

7.3.14

- III -

Publication Release Date:November 2006

Version 1.0

W83877ATF/W83877ATG

7.3.15

7.3.16

DMA Transfers .........................................................................................................................95

Programmed I/O (NON-DMA) Mode.........................................................................................95

7.4

7.5

Extension FDD Mode (EXTFDD)............................................................................................ 95

Extension 2FDD Mode (EXT2FDD)........................................................................................ 95

8. PLUG AND PLAY CONFIGURATION ............................................................................................. 96

9. ACPI /LEGACY FEATURE AND AUTO POWER MANAGEMENT................................................. 97

9.1

9.2

ACPI/Legacy power management .......................................................................................... 97

Device(auto) power management........................................................................................... 97

10. SERIAL IRQ ..................................................................................................................................... 98

10.1 Start Frame ............................................................................................................................. 99

10.2 IRQ/Data Frame...................................................................................................................... 99

10.3 Stop Frame ........................................................................................................................... 101

10.4 Reset and Initialization.......................................................................................................... 101

11. EXTENDED FUNCTION REGISTERS.......................................................................................... 102

11.1 Extended Functions Enable Registers (EFERs)................................................................... 102

11.2 Extended Function Index Registers (EFIRs), Extended Function Data Registers

103

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.2.7

11.2.8

11.2.9

(EFDRs)

Configuration Register 0 (CR0), default = 00H .......................................................................103

Configuration Register 1 (CR1), default = 00H .......................................................................104

Configuration Register 2 (CR2), default = 00H .......................................................................105

Configuration Register 3 (CR3), default = 30H .......................................................................105

Configuration Register 4 (CR4), default = 00H .......................................................................106

Configuration Register 5 (CR5), default = 00H .......................................................................107

Configuration Register 6 (CR6), default = 00H .......................................................................107

Configuration Register 7 (CR7), default = 00H .......................................................................109

Configuration Register 8 (CR8), default = 00H .......................................................................110

11.2.10 Configuration Register 9 (CR9), default = 0DH ......................................................................111

11.2.11 Configuration Register A (CR0A), default = 00H ....................................................................112

11.2.12 Configuration Register B (CR0B), default = 0CH....................................................................112

11.2.13 Configuration Register C (CR0C), default = 28H....................................................................114

11.2.14 Configuration Register D (CR0D), default = A3H ...................................................................115

11.2.15 Configuration Register E (CR0E), Configuration Register F (CR0F) ......................................116

11.2.16 Configuration Register 10 (CR10), default = 00H ...................................................................117

11.2.17 Configuration Register 11 (CR11), default = 00H ...................................................................117

11.2.18 Configuration Register 12 (CR12), default = 00H ...................................................................118

11.2.19 Configuration Register 13 (CR13), default = 00H ...................................................................118

11.2.20 Configuration Register 14 (CR14), default = 00H ...................................................................119

11.2.21 Configuration Register 15 (CR15), default = 00H ...................................................................120

11.2.22 Configuration Register 16 (CR16), default = 04H ...................................................................122

11.2.23 Configuration Register 17 (CR17), default = 00H ...................................................................123

- IV -

W83877ATG Related Products

	W83877ATG
Description	Multifunction Peripheral, CMOS, PQFP100, QFP-100
Is it Rohs certified?	conform to
Maker	Winbond Electronics Corporation
Parts packaging code	QFP
package instruction	QFP, QFP100,.75X.99
Contacts	100
Reach Compliance Code	unknown
Address bus width	16
boundary scan	NO
Bus compatibility	PCI; ISA; IBM PC-AT; PS/2
maximum clock frequency	48 MHz
External data bus width	8
JESD-30 code	R-PQFP-G100
length	20 mm
Number of I/O lines	10
Number of terminals	100
Maximum operating temperature	70 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.75X.99
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	245
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.3 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm
Base Number Matches	1

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