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MC10ELT25D

Description
Differential ECL to TTL Translator
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size49KB,3 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
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MC10ELT25D Overview

Differential ECL to TTL Translator

MC10ELT25D Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMotorola ( NXP )
package instructionSOP, SOP8,.25
Reach Compliance Codeunknow
ECCN codeEAR99
maximum delay4.1 ns
Input propertiesDIFFERENTIAL
Interface integrated circuit typeECL TO TTL TRANSLATOR
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.9 mm
Number of digits1
Number of functions1
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristicsTOTEM-POLE
Output latch or registerNONE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply5 V
Certification statusNot Qualified
Maximum seat height1.75 mm
Nominal supply voltage5 V
surface mountYES
technologyBIPOLAR
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width3.9 mm
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Differential ECL to TTL
Translator
The MC10ELT/100ELT25 is a differential ECL to TTL translator.
Because ECL levels are used a +5V, -5.2V (or -4.5V) and ground are
required. The small outline 8-lead SOIC package and the single gate of
the ELT25 makes it ideal for those applications where space,
performance and low power are at a premium. Because the mature
MOSAIC 1.5 process is used, low cost can be added to the list of
features.
The VBB output allows the ELT25 to also be used in a single-ended
input mode. In this mode the VBB output is tied to the IN input for a
non-inverting buffer or the IN input for an inverting buffer. If used the VBB
pin should be bypassed to ground via a 0.01µF capacitor.
The ELT25 is available in both ECL standards: the 10ELT is compatible
with MECL 10H logic levels while the 100ELT is compatible with ECL
100K logic levels.
MC10ELT25
MC100ELT25
8
1
2.6ns Typical Propagation Delay
Differential ECL Inputs
Small Outline SOIC Package
24mA TTL Outputs
Flow Through Pinouts
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VEE 1
TTL
ECL
D0
3
8
VCC
PIN
D
Q
VCC
VEE
VBB
GND
PIN DESCRIPTION
FUNCTION
Diff ECL Inputs
TTL Output
Positive Supply
Negative Supply
Reference Output
Ground
D0
2
7
Q0
6
NC
VBB
4
5
GND
1/95
©
Motorola, Inc. 1996
3–1
REV 2

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Description Differential ECL to TTL Translator Differential ECL to TTL Translator Differential ECL to TTL Translator Differential ECL to TTL Translator
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