MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage 2:8 Differential
Fanout Buffer
ECL/PECL Compatible
MC100LVE310
MC100E310
The MC100LVE310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device features
fully differential clock paths to minimize both device and system skew.
The LVE310 offers two selectable clock inputs to allow for redundant or
test clocks to be incorporated into the system clock trees. The
MC100E310 is pin compatible to the National 100310 device. The
MC100LVE310 works from a –3.3V supply while the MC100E310
provides identical function and performance from a standard –4.5V 100E
voltage supply.
LOW VOLTAGE
2:8 DIFFERENTIAL
FANOUT BUFFER
•
•
•
•
•
Dual Differential Fanout Buffers
200ps Part–to–Part Skew
50ps Output–to–Output Skew
Low Voltage ECL/PECL Compatible
28–lead PLCC Packaging
For applications which require a single–ended input, the VBB reference
voltage is supplied. For single–ended input applications the VBB
reference should be connected to the CLK input and bypassed to ground
FN SUFFIX
via a 0.01µf capacitor. The input signal is then driven into the CLK input.
PLASTIC PACKAGE
To ensure that the tight skew specification is met it is necessary that
CASE 776–02
both sides of the differential output are terminated into 50Ω, even if only
one side is being used. In most applications all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine
pairs are used it is necessary to terminate at least the output pairs
adjacent to the output pair being used in order to maintain minimum skew.
Failure to follow this guideline will result in small degradations of
propagation delay (on the order of 10–20ps) of the outputs being used,
while not catastrophic to most designs this will result in an increase in
skew. Note that the package corners isolate outputs from one another
such that the guideline expressed above holds only for outputs on the
same side of the package.
The MC100LVE310, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the
LVE310 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE310’s
performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line
terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage
of VCC–2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note
AN1406/D.
7/95
©
Motorola, Inc. 1996
4–1
REV 0.1
MC100LVE310 MC100E310
Q0
25
VEE
CLK_SEL
CLKa
VCC
CLKa
VBB
CLKb
26
27
28
1
2
3
4
5
CLKb
6
NC
7
8
9
10
Q6
11
Q6
Q0
24
Q1 VCCO Q1
23
22
21
Q2
20
Q2
19
18
17
16
Q3
PIN NAMES
Q3
Pins
Q4
VCCO
Q4
Q5
Q5
CLK_SEL
0
1
Input Clock
CLKa Selected
CLKb Selected
CLKa, CLKb
Q0:7
VBB
CLK_SEL
Function
Differential Input Pairs
Differential Outputs
VBB Output
Input Clock Select
Pinout: 28–Lead PLCC
(Top View)
15
14
13
12
Q7 VCCO Q7
LOGIC SYMBOL
Q0
Q0
Q1
Q1
Q2
Q2
CLKa
CLKa
CLKb
CLKb
CLK_SEL
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
VBB
MOTOROLA
4–2
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MC100LVE310 MC100E310
MC100LVE310
ECL DC CHARACTERISTICS
–40°C
Symbol
VOH
VOL
VIH
VIL
VBB
VEE
IIH
IEE
Characteristic
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Output Reference
Voltage
Power Supply Voltage
Input HIGH Current
Power Supply Current
55
Min
–1.085
–1.830
–1.165
–1.810
–1.38
–3.0
Typ
–1.005
–1.695
Max
–0.880
–1.555
–0.880
–1.475
–1.26
–3.8
150
60
55
Min
–1.025
–1.810
–1.165
–1.810
–1.38
–3.0
0°C
Typ
–0.955
–1.705
Max
–0.880
–1.620
–0.880
–1.475
–1.26
–3.8
150
60
55
Min
–1.025
–1.810
–1.165
–1.810
–1.38
–3.0
25°C
Typ
–0.955
–1.705
Max
–0.880
–1.620
–0.880
–1.475
–1.26
–3.8
150
60
65
Min
–1.025
–1.810
–1.165
–1.810
–1.38
–3.0
85°C
Typ
–0.955
–1.705
Max
–0.880
–1.620
–0.880
–1.475
–1.26
–3.8
150
70
Unit
V
V
V
V
V
V
µA
mA
MC100LVE310
PECL DC CHARACTERISTICS
–40°C
Symbol
VOH
VOL
VIH
VIL
VBB
VCC
IIH
IEE
Characteristic
Output HIGH Voltage
1
Output LOW Voltage
1
Input HIGH Voltage
1
Input LOW Voltage
1
Output Reference
Voltage
1
Power Supply Voltage
Input HIGH Current
Power Supply Current
55
Min
2.215
1.47
2.135
1.490
1.92
3.0
Typ
2.295
1.605
Max
2.42
1.745
2.420
1.825
2.04
3.8
150
60
55
Min
2.275
1.490
2.135
1.490
1.92
3.0
0°C
Typ
2.345
1.595
Max
2.420
1.680
2.420
1.825
2.04
3.8
150
60
55
Min
2.275
1.490
2.135
1.490
1.92
3.0
25°C
Typ
2.345
1.595
Max
2.420
1.680
2.420
1.825
2.04
3.8
150
60
65
Min
2.275
1.490
2.135
1.490
1.92
3.0
85°C
Typ
2.345
1.595
Max
2.420
1.680
2.420
1.825
2.04
3.8
150
70
Unit
V
V
V
V
V
V
µA
mA
1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
MC100LVE310
AC CHARACTERISTICS
(VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
–40°C
Symbol
tPLH
tPHL
tskew
VPP
VCMR
tr/tf
Characteristic
Propagation Delay to Output
IN (differential)
IN (single–ended)
Within–Device Skew
Part–to–Part Skew (Diff)
Minimum Input Swing
Common Mode Range
Output Rise/Fall Time
500
–1.5
200
–0.4
600
Min
525
500
Typ
Max
725
750
75
250
500
–1.5
200
–0.4
600
Min
550
525
0°C
Typ
Max
750
775
75
200
500
–1.5
200
–0.4
600
Min
550
550
25°C
Typ
Max
750
800
50
200
500
–1.5
200
–0.4
600
Min
575
600
85°C
Typ
Max
775
850
50
200
ps
mV
V
ps
Unit
ps
Note 1
Note 2
Note 3
Note 4
Note 5
20%–80%
Condition
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See
Definitions and Testing of ECLinPS AC Parameters
in Chapter 1 (page 1–12) of the Motorola High Performance
ECL Data Book (DL140/D).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters
in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D).
3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the LVE310 as a differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
ECLinPS and ECLinPS Lite
DL140 — Rev 3
4–3
MOTOROLA
MC100LVE310 MC100E310
MC100E310
ECL DC CHARACTERISTICS
–40°C
Symbol
VOH
VOL
VIH
VIL
VBB
VEE
IIH
IEE
Characteristic
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Output Reference
Voltage
Power Supply Voltage
Input HIGH Current
Power Supply Current
55
Min
–1.085
–1.830
–1.165
–1.810
–1.38
–5.25
Typ
–1.005
–1.695
Max
–0.880
–1.555
–0.880
–1.475
–1.26
–4.2
150
60
55
Min
–1.025
–1.810
–1.165
–1.810
–1.38
–5.25
0°C
Typ
–0.955
–1.705
Max
–0.880
–1.620
–0.880
–1.475
–1.26
–4.2
150
60
55
Min
–1.025
–1.810
–1.165
–1.810
–1.38
–5.25
25°C
Typ
–0.955
–1.705
Max
–0.880
–1.620
–0.880
–1.475
–1.26
–4.2
150
60
65
Min
–1.025
–1.810
–1.165
–1.810
–1.38
–5.25
85°C
Typ
–0.955
–1.705
Max
–0.880
–1.620
–0.880
–1.475
–1.26
–4.2
150
70
Unit
V
V
V
V
V
V
µA
mA
MC100E310
PECL DC CHARACTERISTICS
–40°C
Symbol
VOH
VOL
VIH
VIL
VBB
VCC
IIH
IEE
Characteristic
Output HIGH Voltage
1
Output LOW Voltage
1
Input HIGH Voltage
1
Input LOW Voltage
1
Output Reference
Voltage
1
Power Supply Voltage
Input HIGH Current
Power Supply Current
55
Min
3.915
3.170
3.835
3.190
3.62
4.75
Typ
3.995
3.305
Max
4.12
3.445
4.12
3.525
3.74
5.25
150
60
55
Min
3.975
3.19
3.835
3.190
3.62
4.75
0°C
Typ
4.045
3.295
Max
4.12
3.38
4.12
3.525
3.74
5.25
150
60
55
Min
3.975
3.19
3.835
3.190
3.62
4.75
25°C
Typ
4.045
3.295
Max
4.12
3.38
4.12
3.525
3.74
5.25
150
60
65
Min
3.975
3.19
3.835
3.190
3.62
4.75
85°C
Typ
4.045
3.295
Max
4.12
3.38
4.12
3.525
3.74
5.25
150
70
Unit
V
V
V
V
V
V
µA
mA
1. These values are for VCC = 5.0V. Level Specifications will vary 1:1 with VCC.
MC100E310
AC CHARACTERISTICS
(VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
–40°C
Symbol
tPLH
tPHL
tskew
VPP
VCMR
tr/tf
Characteristic
Propagation Delay to Output
IN (differential)
IN (single–ended)
Within–Device Skew
Part–to–Part Skew (Diff)
Minimum Input Swing
Common Mode Range
Output Rise/Fall Time
500
–1.5
200
–0.4
600
Min
525
500
Typ
Max
725
750
75
250
500
–1.5
200
–0.4
600
Min
550
525
0°C
Typ
Max
750
775
75
200
500
–1.5
200
–0.4
600
Min
550
550
25°C
Typ
Max
750
800
50
200
500
–1.5
200
–0.4
600
Min
575
600
85°C
Typ
Max
775
850
50
200
ps
mV
V
ps
Unit
ps
Note 1
Note 2
Note 3
Note 4
note 5
20%–80%
Condition
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See
Definitions and Testing of ECLinPS AC Parameters
in Chapter 1 (page 1–12) of the Motorola High Performance
ECL Data Book (DL140/D).
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See
Definitions and Testing of ECLinPS AC Parameters
in Chapter 1 (page 1–12) of the Motorola High Performance ECL Data Book (DL140/D).
3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device.
4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the E310 as a differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
MOTOROLA
4–4
ECLinPS and ECLinPS Lite
DL140 — Rev 3
MC100LVE310 MC100E310
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
0.007 (0.180)
U
T L –M
M
B
-N-
Y BRK
M
S
N
S
S
0.007 (0.180)
T L –M
N
S
D
Z
-L-
-M-
W
28
1
D
X
VIEW D-D
G1
0.010 (0.250)
S
V
T L –M
S
N
S
A
Z
R
0.007 (0.180)
0.007 (0.180)
M
T L –M
T L –M
S
N
N
S
H
S
0.007 (0.180)
M
T L –M
S
N
S
M
S
C
E
G
G1
0.010 (0.250)
S
K1
0.004 (0.100)
J
-T-
SEATING
PLANE
K
F
VIEW S
0.007 (0.180)
M
VIEW S
T L –M
S
T L –M
S
N
S
N
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
—
0.025
—
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
—
0.020
2°
10°
0.410 0.430
0.040
—
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
—
0.64
—
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
—
0.50
2°
10°
10.42 10.92
1.02
—
ECLinPS and ECLinPS Lite
DL140 — Rev 3
4–5
MOTOROLA
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