1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
2. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
3. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75
mV to that IN/IN transition.
4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than
±75
mV to that IN/IN transition.
5. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of
asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for
increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions
and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB
the device is guaranteed to be monotonic over all specified environmental conditions and process variation.
8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.
MOTOROLA
2–2
ECLinPS and ECLinPS Lite
DL140 — Rev 4
MC10E195 MC100E195
ADDRESS BUS (A0–A6)
A7
D2
D3
D4
D5
D6
D7
D2
D3
D4
D5
D6
D7
VCC
VCCO
Q
CASCADE
CASCADE
SET MAX
Q
VCCO
OUTPUT
SET MIN
BIT 6
Q5
D6
LEN
Reset Reset
Q6
D1
D0
LEN
VEE
IN
INPUT
CASCADE
CASCADE
SET MAX
IN
SET MIN
VBB
EN
D1
E195
Chip #1
D0
VCC
VCCO
Q
Q
VCCO
LEN
VEE
IN
IN
VBB
E195
Chip #2
Figure 1. Cascading Interconnect Architecture
Cascading Multiple E195’s
To increase the programmable range of the E195 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E195’s without the need for any
external gating. Furthermore this capability requires only one
more address line per added E195. Obviously cascading
multiple PDC’s will result in a larger programmable range
however this increase is at the expense of a longer minimum
delay.
Figure 1 illustrates the interconnect scheme for cascading
two E195’s. As can be seen, this scheme can easily be
expanded for larger E195 chains. The D7 input of the E195 is
the cascade control pin. With the interconnect scheme of
Figure 1 when D7 is asserted it signals the need for a larger
programmable range than is achievable with a single device.
An expansion of the latch section of the block diagram is
pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D7 of
chip #1 above is low the cascade output will also be low while
the cascade bar output will be a logical high. In this condition
the SET MIN pin of chip #2 will be asserted and thus all of the
latches of chip #2 will be reset and the device will be set at its
minimum delay. Since the RESET and SET inputs of the
latches are overriding any changes on the A0–A6 address bus
will not affect the operation of chip #2.
TO SELECT MULTIPLEXERS
Chip #1 on the other hand will have both SET MIN and SET
MAX de-asserted so that its delay will be controlled entirely by
the address bus A0–A6. If the delay needed is greater than
can be achieved with 31.75 gate delays (1111111 on the
A0–A6 address bus) D7 will be asserted to signal the need to
cascade the delay to the next E195 device. When D7 is
asserted the SET MIN pin of chip #2 will be de-asserted and
the delay will be controlled by the A0–A6 address bus. Chip #1
on the other hand will have its SET MAX pin asserted resulting
in the device delay to be independent of the A0–A6 address
bus.
When the SET MAX pin of chip #1 is asserted the D0 and D1
latches will be reset while the rest of the latches will be set. In
addition, to maintain monotonicity an additional gate delay is
selected in the cascade circuitry. As a result when D7 of chip
#1 is asserted the delay increases from 31.75 gates to 32
gates. A 32 gate delay is the maximum delay setting for the
E195.
To expand this cascading scheme to more devices one
simply needs to connect the D7 input and CASCADE outputs
of the current most significant E195 to the new most significant
E195 in the same manner as pictured in Figure 1. The only
addition to the logic is the increase of one line to the address
bus for cascade control of the second PDC.
BIT 0
D0
LEN
Reset Reset
Q0
BIT 1
D1
LEN
Reset Reset
Q1
D2
BIT 2
Q2
BIT 3
D3
LEN
Reset Reset
Q3
D4
BIT 4
Q4
D5
BIT 5
EN
BIT 7
CASCADE
D7
LEN
Reset Reset
Q7
CASCADE
LEN
Reset Reset
LEN
Reset Reset
LEN
Reset Reset
SET MIN
SET MAX
Figure 2. Expansion of the Latch Section of the E195 Block Diagram
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–3
MOTOROLA
MC10E195 MC100E195
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
0.007 (0.180)
U
T L –M
M
B
-N-
Y BRK
M
S
N
S
S
0.007 (0.180)
T L –M
N
S
D
Z
-L-
-M-
W
28
1
D
X
VIEW D-D
G1
0.010 (0.250)
S
V
T L –M
S
N
S
A
Z
R
0.007 (0.180)
0.007 (0.180)
M
T L –M
T L –M
S
N
N
S
H
S
0.007 (0.180)
M
T L –M
S
N
S
M
S
C
E
G
G1
0.010 (0.250)
S
K1
0.004 (0.100)
J
-T-
SEATING
PLANE
K
F
VIEW S
0.007 (0.180)
M
VIEW S
T L –M
S
T L –M
S
N
S
N
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
—
0.025
—
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
—
0.020
2°
10°
0.410 0.430
0.040
—
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
—
0.64
—
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
—
0.50
2°
10°
10.42 10.92
1.02
—
MOTOROLA
2–4
ECLinPS and ECLinPS Lite
DL140 — Rev 4
MC10E195 MC100E195
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed:
Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
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