SL28548-2
Clock Generator for Intel
®
Crestline Chipset
Features
• Compliant to Intel
®
CK505
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Scalable low voltage VDD_IO (3.3V to 1.05V)
• Differential CPU clocks with selectable frequency
• • 8-step slew rate control for single-ended clock outputs
• 100 MHz Differential SRC clocks
• 100 MHz Differential LCD clock
• 96 MHz Differential DOT clock
• 48 MHz USB clocks
CPU
SRC
PCI REF DOT96 USB_48 LCD
x6
x1
x1
x1
x1
27M
x2
x2 / x3 x7/11
• 33 MHz PCI clock
• 27 MHz Video clocks
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
•
64-pin QFN/TSSOP packages
Block Diagram
Rev 1.5 July 28, 2008
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 32
www.SpectraLinear.com
SL28548-2
Pin Configuration
64-Pin TSSOP
64-Pin QFN
QFN Pin Definitions
Pin No.
1
2
3
4
5
Xout
Xin
VDD_REF
REF0 / FSC / TEST_SEL
Name
VSS_REF
Type
GND
I
PWR
I/O
Ground for outputs.
14.318 MHz Crystal input.
3.3V Power supply for outputs and maintains SMBUS registers during power
down.
Fixed 14.318 clock output/3.3V-tolerant input for CPU frequency selection/
Selects test mode if pulled to V
IHFS_C
when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for V
ILFS_C
, V
IMFS_C
, V
IHFS_C
specifica-
tions.
SMBus compatible SDATA.
SMBus compatible SCLOCK.
O, SE
14.318 MHz Crystal output.
Description
6
7
SDATA
SCLK
I/O
I
Rev 1.5 July 28, 2008
Page 2 of 32
SL28548-2
QFN Pin Definitions
(continued)
Pin No.
8
Name
PCI0 / CR#_A
Type
Description
I/O, SE
33 MHz Clock/3.3V Clock Request # Input
Mappable via I2C to control either SRC 0 or SRC 2. Default PCI0.
To configure this pin to serve as a Clock Request pin for either SRC pair 2 or pair
0 using the CR#_A_EN bit located in byte 5 bit 7, first disable PCI output (Hi-z) in
byte 2, bit 1.
0 = PCI0 enabled (default)
1= CR#_A enabled.
Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6:
0 = CR#_A controls SRC0 pair (default)
1= CR#_A controls SRC2 pair
PWR
3.3V power supply for PCI PLL
I/O, SE
33 MHz Clock/3.3V Clock Request # Input
Mappable via I2C to control either SRC 1 or SRC 4. Default PCI1.
To configure this pin to serve as a Clock Request pin for either SRC pair 1 or pair
4 using the CR#_B_EN bit located in byte 5, bit 5, first disable PCI output (Hi-z) in
byte 2, bit 1.
0 = PCI1 enabled (default)
1= CR#_B enabled.
Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4:
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
I/O, SE
33 MHz Clock output/3.3V-tolerance input for enabling Trusted Mode
Sampled at CKPWRGD assertion:
0 = Normal mode, 1 = Trusted mode (no overclocking)
O, SE
33 MHz Clock output
I/O, SE
33 MHz Clock output/3.3V-tolerant input for selecting graphic clock source
on pin 20, 21, 24 and 25
Sampled on CKPWRGD assertion;
GCLK_SEL
0
1
Pin 20
SRCT0
Pin 21
SRCC0
Pin 24
27M_NSS
Pin 25
27M_SS
9
10
VDD_PCI
PCI1 / CR#_B
11
PCI2 / TME
12
13
PCI3
PCI4 / GCLK_SEL
DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C
14
PCIF0 / ITP_EN
I/O, SE
33 MHz free running clock output/3.3V LVTTL input to enable SRC8 or
CPU2_ITP
(sampled on the CKPWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
GND
PWR
I/O
GND
PWR
Ground for outputs.
3.3V power supply for outputs and PLL.
Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
3.3V-1.25V power supply for outputs
15
16
17
18
19
20
21
VSS_PCI
VDD_48
USB_48 / FSA
VSS_48
VDD_IO
SRCT0 / DOT96T
SRCC0 / DOT96C
O, DIF
True 100 MHz Differential serial reference clocks/Fixed True 96 MHz clock
output.
Selected via GCLK_SEL at CKPWRGD assertion
O, DIF
Complementary 100 MHz Differential serial reference clocks/Fixed
complement 96 MHz clock output.
Selected via GCLK_SEL at CKPWRGD assertion
GND
PWR
Ground for outputs.
3.3V Power supply for PLL3.
22
23
24
VSS_IO
VDD_PLL3
SRCT1 /
LCDT_100/27M_NSS
O, DIF,
True 100 MHz differential serial reference clock output/True 100 MHz LCD
SE
video clock output / Non spread 27-MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
Rev 1.5 July 28, 2008
Page 3 of 32
SL28548-2
QFN Pin Definitions
(continued)
Pin No.
25
Name
SRCC1 /
LCDC_100/27M_SS
VSS_PLL3
VDD_PLL3_IO
SRCT2 / SATAT
SRCC2 / SATAC
VSS_SRC
SRCT3 / CR#_C
Type
Description
O, DIF,
Complementary 100 MHz differential serial reference clock output/Comple-
SE
mentary 100 MHz LCD video clock output /Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
GND
PWR
Ground for PLL3.
3.3V-1.25V power supply for outputs.
26
27
28
29
30
31
O, DIF
True 100 MHz differential serial reference clock output.
O, DIF
Complementary 100 MHz differential serial reference clock output.
GND
I/O,
DIF
Ground for outputs.
True 100 MHz differential serial reference clock output /3.3V Clock Request
#_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
Complementary 100 MHz differential serial reference clock output/3.3V Clock
Request #_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
3.3V-1.25V Power supply for outputs.
32
SRCC3 / CR#_D
I/O,
DIF
33
34
35
36
37
38
39
VDD_SRC_IO
SRCT4
SRCC4
VSS_SRC
SRCT9
SRCC9
SRCC11/ CR#_G
PWR
O, DIF
True 100 MHz differential serial reference clocks.
O, DIF
Complementary 100 MHz differential serial reference clocks.
GND
Ground for outputs.
O, DIF
True 100 MHz differential serial reference clocks.
O, DIF
Complementary 100 MHz differential serial reference clocks.
I/O,
DIF
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_G Input.
Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
Complementary 100 MHz Differential serial reference clocks/3.3V CR#_H
Input.
Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
40
SRCT11/ CR#_H
41
42
43
44
SRCT10
SRCC10
VDD_SRC_IO
CPU_STOP#
O, DIF
True 100 MHz Differential serial reference clocks.
O, DIF
Complementary 100 MHz Differential serial reference clocks.
PWR
I
3.3V-1.25V power supply for outputs.
3.3V-tolerant input for stopping CPU outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See
Figure 13
for more information.
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See
Figure 13
for more information.
3.3V power supply for SRC PLL.
45
PCI_STOP#
I
46
47
48
49
50
VDD_SRC
SRCC6
SRCT6
VSS_SRC
SRCC7/ CR#_E
PWR
O, DIF
Complementary 100 MHz Differential serial reference clocks.
O, DIF
True 100 MHz Differential serial reference clocks.
GND
I/O,
DIF
Ground for outputs.
Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
Rev 1.5 July 28, 2008
Page 4 of 32
SL28548-2
QFN Pin Definitions
(continued)
Pin No.
51
Name
SRCT7/ CR#_F
Type
I/O,
DIF
PWR
Description
True 100 MHz differential serial reference clocks/3.3V CR#_F Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
3.3V-1.25V Power supply for outputs.
52
53
VDD_SRC_IO
SRCC8 / CPUC2_ITP
O, DIF
Selectable complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
O, DIF
Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
NC
PWR
No connect.
3.3V-1.25V Power supply for outputs.
54
SRCT8 / CPUT2_ITP,
55
56
57
58
59
60
61
62
63
NC
VDD_CPU_IO
CPUC1
CPUT1
VSS_CPU
CPUC0
CPUT0
VDD_CPU
CKPWRGD / PWRDWN#
O, DIF
Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
O, DIF
True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
GND
Ground for outputs.
O, DIF
Complement differential CPU clock outputs.
O, DIF
True differential CPU clock outputs.
PWR
I
3.3V Power supply for CPU PLL.
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode.
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
64
FSB / TEST_MODE
I
TSSOP Pin Definitions
Pin No.
1
Name
PCI0 / CR#_A
Type
Description
I/O, SE
33 MHz clock/3.3V Clock Request # Input.
Selected via CR#_A_EN bit located in byte 5 bit 7.
The CR#_A_SEL bit in byte 5 bit 6 will select to control SRC0 or SRC2 when
asserted.
PWR
3.3V Power supply for PCI PLL.
I/O, SE
33 MHz Clock/3.3V Clock Request # Input.Selected via CR#_B_EN bit located
in byte 5 bit 5.
The CR#_B_SEL bit in byte 5 bit 4 will select to control SRC1 or SRC4 when
asserted.
I/O, SE
33 MHz clock output / 3.3V-tolerance input for enabling trusted mode
Sampled at CKPWRGD assertion:
0 = Normal mode, 1 = Trusted mode (no overclocking)
O, SE
33 MHz clock output
2
3
VDD_PCI
PCI1 / CR#_B
4
PCI2 / TME
5
PCI3
Rev 1.5 July 28, 2008
Page 5 of 32
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