XRT7296
PIN CONFIGURATION
#
==0
==0
*
=
<
0
7
#
57
7 =
=
40<
79
&
)
"
!
%
!
"
)
&
%
!
"
)
&
7
0
<
<
0
75
57
@
0
@
75
@=
#=
0=
7 5
#
==0
==0
*
=
<
0
7
#
57
7 =
=
40<
79
&
)
"
!
%
!
"
)
&
%
!
"
)
&
7
0
<
<
0
75
57
@
0
@
75
@=
#=
0=
7 5
28 Lead PDIP (0.600”)
28 Lead SOJ (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
Symbol
#
==0
==0
Type
Description
Receive Clock Input.
Remote Loop Back.
Local Loop Back.
/
,
,
0= 7 5
/
+-
==0 ==0 11 ,+
*
DS3, STS-1 or E3 Select Pin
:4
Transmit All Ones Select
5 V Digital Supply
Transmit Positive Data
Transmit Negative Data.
Transmit Clock
. 0 7
Digital Ground
Encoder Disable.
11
1 3+
49 :4
/ ., /
, +
*
3- =
>,
1 ,
3
11 . 0 7
+
-
*
/
Decoder Disable
!
*
=
<
0
7
#
57
7 =
&
)
"
!
%
=
XRT7296
PIN DESCRIPTION (CONT’D)
Pin #
Symbol
40<
Type
=
Description
Bipolar Violation Output
7 +
Receive Binary Data.
Receive Negative Data.
Receive Positive Data
Receive Clock Output
Driver Monitor Output.
!±
# /+ /;
@=
11 ,
+
1
A
@
+
/
Monitor Ring Input
@
+ .
75 / 3
/
/
1 . +
.+*
Monitor Tip Input
@
+ .
0 / 3
/
/
1 . +
.+,
Analog Ground
=
=
*
Transmit Ring Output
Transmit Tip Output.
5V Analog Supply (± 5%)
Transmit Level Select.
1
,
,
+ +
,
0
75 / 3
3-
1 H11H
H+ 2H 1
,
+
.
A < H11H H+ 2H
3
+ 2
81
1
/3+
+
1 +
1 .
A < ,
3
H+ 2H '
1
81
1
/3+
+
1
1 .
+
1 & .
A < - 3
H11H
1
,
,
,+
.
1
"%)
/
2++
1
,+
81
1
/3+
+
1
1 & .
1
A < ,
3
H11H '
Note:
This input pin is only active, for DS3 and STS•1 applications.
)
"
!
0
7
In-circuit Testing.
Receive Positive Data
#
Receive Negative Data
#
&
)
"
!
%
&
79
7 5
0=
#=
@=
@
75
@
0
57
75
0
<
<
=
=
=
=
=
Note
1
If a bipolar violation occurs, RPOS and RNEG can correspond to the decoded versions of RNDATA and RPDATA respectively. If
DECODIS is high, RPOS and RNEG always track RPDATA and RNDATA respectively.
XRT7296
ELECTRICAL CHARACTERISTICS
(See Figure 8 )
Test Conditions: V
DD
= 5V
±
5%, T
A
= -40C to +85C, unless otherwise specified. All timing characteristics
are measured with 10pF loading.
Symbol
Parameter
+-
,
,
<
<
:
<
=
<
=:
"&
&
&
&
)
&
&
&&
Min.
&
"
Typ.
&
&
Max.
&&
&
Units
.
.
.
AC Electrical Characteristics
DC Electrical Characteristics
<
<
&&
<
J "
57
<
* &
*&
&
<
<
±
*&
<
<
<
<
<
$
$
=?
K*
=?
K
Notes:
1
When the encoder is enabled, a handling delay of four and a half TCLK clock cycles for B3ZS and five and half clock cycles for HDB3
always exists between TPDATA/TNDATA and TTIP/TRING. The handling delay is reduced to two clock cycles when the encoder
is disabled.
2
When the decoder is enabled, a handling delay of six and a half RCLK clock cycles will always exist between RPDATA/RNDATA
and RPOS/RNEG/RNRZ. The handling delay is reduced to one and half RCLK clock cycles when the decoder is disabled.
3
Supply current is measured with transmitter sending all ones AMI signal and with Transmit Level (TXLEV) set to high.
4
All inputs except pin 19, 20 and pin 26.
Specifications are subject to change without notice
&
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