MBM29LV160B-80PFTN datasheet, PDF

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MBM29LV160B-80PFTN: Description16M (2M xⅴ 8/1M x 16) BIT; Categorystorage storage; File Size453KB，60 Pages; ManufacturerFUJITSU; Websitehttp://edevice.fujitsu.com/fmd/en/index.html

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MBM29LV160B-80PFTN Overview

16M (2M xⅴ 8/1M x 16) BIT

MBM29LV160B-80PFTN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	FUJITSU
Objectid	1491418309
Parts packaging code	TSOP1
package instruction	PLASTIC, TSOP1-48
Contacts	48
Reach Compliance Code	unknow
ECCN code	EAR99
compound_id	9911441
Maximum access time	80 ns
Other features	CONFIGURABLE AS 1M X 16
Spare memory width	8
startup block	BOTTOM
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	18.4 mm
memory density	16777216 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	1,2,1,31
Number of terminals	48
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
organize	1MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.035 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
switch bit	YES
type	NOR TYPE
width	12 mm

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20846-4E

FLASH MEMORY

CMOS

16M (2M

8/1M

16) BIT

MBM29LV160T

-80/-90/-12

/MBM29LV160B

-80/-90/-12

FEATURES

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)

46-pin SON (Package suffix: PN)

48-pin CSOP (Package suffix: PCV)

48-ball FBGA (Package suffix: PBT)

• Minimum 100,000 program/erase cycles

• High performance

80 ns maximum access time

• Sector erase architecture

One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode

One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded program

Algorithms

Automatically programs and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switches themselves to low power mode

• Low V

write inhibit

≤

2.5 V

(Continued)

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

MBM29LV160T

-80/-90/-12

/MBM29LV160B

-80/-90/-12

GENERAL DESCRIPTION

The MBM29LV160T/B is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words

of 16 bits each. The MBM29LV160T/B is offered in a 48-pin TSOP (I), 46-pin SON, 48-pin CSOP and 48-ball

FBGA packages. The device is designed to be programmed in-system with the standard system 3.0 V V

supply.

12.0 V V

and 5.0 V V

are not required for write or erase operations. The device can also be reprogrammed

in standard EPROM programmers.

The standard MBM29LV160T/B offers access times of 80 ns and 120 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write

enable (WE), and output enable (OE) controls.

The MBM29LV160T/B is pin and command set compatible with JEDEC standard E

PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the device is

similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV160T/B is programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the device automatically times the erase pulse widths and

verifies proper cell margins.

Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29LV160T/B is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

comleted, the device internally resets to the read mode.

The MBM29LV160T/B also has a hardware RESET pin. When this pin is driven low, execution of any Embedded

Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the

read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during

the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read

mode and will have erroneous data stored in the address locations being programmed or erased. These locations

need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up

firmware from the Flash memory.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The MBM29LV160T/B memory electrically erases all bits within

a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a

time using the EPROM programming mechanism of hot electron injection.

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