MBM29LV002TC-70PTN datasheet, PDF

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MBM29LV002TC-70PTN: Description2M (256K x 8) BIT; Categorystorage storage; File Size278KB，52 Pages; ManufacturerFUJITSU; Websitehttp://edevice.fujitsu.com/fmd/en/index.html

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MBM29LV002TC-70PTN Overview

2M (256K x 8) BIT

MBM29LV002TC-70PTN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	FUJITSU
Parts packaging code	TSOP1
package instruction	PLASTIC, TSOP1-40
Contacts	40
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	70 ns
Other features	MINIMUM 100000 PROGRAM/ERASE CYCLES
startup block	TOP
command user interface	YES
Data polling	YES
JESD-30 code	R-PDSO-G40
JESD-609 code	e0
length	18.4 mm
memory density	2097152 bi
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	1,2,1,3
Number of terminals	40
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP40,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.035 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
switch bit	YES
type	NOR TYPE
width	10 mm

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20863-3E

FLASH MEMORY

CMOS

2M (256K

8) BIT

MBM29LV002TC

70/-90/-12

/MBM29LV002BC

-70/-90/-12

FEATURES

• Single 3.0 V read, program, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

• Compatible with JEDEC-standard world-wide pinouts

40-pin TSOP(I) (Package suffix: PTN – Normal Bend Type, PTR – Reversed Bend Type)

40-pin SON (Package suffix: PNS)

• Minimum 100,000 program/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program

Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode

• Low V

write inhibit

≤

2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data in another sector within the same device

• Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Sector Protection Set function by Extended sector protection command

• Temporary sector unprotection

Temporary sector unprotection via the RESET pin

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

MBM29LV002TC

-70/-90/-12

/MBM29LV002BC

-70/-90/-12

GENERAL DESCRIPTION

The MBM29LV002TC/BC are a 2M-bit, 3.0 V-only Flash memory organized as 256K bytes of 8 bits each. The

MBM29LV002TC/BC are offered in a 40-pin TSOP(I) and 40-pin SON packages. These devices are designed

to be programmed in-system with the standard system 3.0 V V

supply. 12.0 V V

and 5.0 V V

are not required

for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.

The standard MBM29LV002TC/BC offer access times 70 ns and 120 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),

write enable (WE), and output enable (OE) controls.

The MBM29LV002TC/BC are pin and command set compatible with JEDEC standard E

PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as

input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the devices

is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV002TC/BC are programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the devices automatically time the erase pulse widths and

verify proper cell margin.

Any individual sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29LV002TC/BC are erased when shipped from the

factory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the devices internally reset to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E

PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The MBM29LV002TC/BC memories electrically erase the entire chip

or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte

at a time using the EPROM programming mechanism of hot electron injection.

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