MBM29F160TE-70 datasheet, PDF - EEWORLD Datasheet

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MBM29F160TE-70: Description2M X 8 FLASH 5V PROM, 70 ns, PDSO48; Categorystorage; File Size241KB，53 Pages; ManufacturerFUJITSU; Websitehttp://edevice.fujitsu.com/fmd/en/index.html

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MBM29F160TE-70 Overview

2M X 8 FLASH 5V PROM, 70 ns, PDSO48

MBM29F160TE-70 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	48
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
maximum access time	70 ns
Processing package description	Plastic, TSOP1-48
state	DISCONTINUED
Craftsmanship	CMOS
packaging shape	Rectangle
Package Size	SMALL OUTLINE, THIN PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	pair
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	8
organize	2M × 8
storage density	1.68E7 deg
operating mode	ASYNCHRONOUS
Number of digits	2.10E6 words
Number of digits	2M
Memory IC type	FLASH 5V programmable read-only memory
serial parallel	parallel

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20879-2E

FLASH MEMORY

CMOS

16M (2M

8/1M

16) BIT

MBM29F160TE/BE

-55/-70/-90

GENERAL DESCRIPTION

The MBM29F160TE/BE is a 16M-bit, 5.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words

of 16 bits each. The MBM29F160TE/BE is offered in a 48-pin TSOP (I) package. The device is designed to be

programmed in-system with the standard system 5.0 V V

supply. 12.0 V V

is not required for write or erase

operations. The device can also be reprogrammed in standard EPROM programmers.

The standard MBM29F160TE/BE offers access times of 55 ns, 70 ns and 90 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write

enable (WE), and output enable (OE) controls.

The MBM29F160TE/BE is pin and command set compatible with JEDEC standard E

PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase operations. Reading data out of the device is similar

to reading from 12.0 V Flash or EPROM devices.

(Continued)

PRODUCT LINE UP

Part No.

Ordering Part No.

= 5.0 V±5%

= 5.0 V±10%

-55

—

MBM29F160TE/160BE

—

-70

—

-90

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

PACKAGES

48-pin plastic TSOP (I)

Marking Side

(FPT-48P-M19)

(FPT-48P-M20)

MBM29F160TE

-55/-70/-90

/MBM29F160BE

-55/-70/-90

(Continued)

The MBM29F160TE/BE is programmed by executing the program command sequence. This will invoke the

Embedded Program

* Algorithm which is an internal algorithm that automatically times the program pulse

widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5

seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded

Erase

* Algorithm which is an internal algorithm that automatically preprograms the array if it is not already

programmed before executing the erase operation. During erase, the device automatically times the erase pulse

widths and verifies proper cell margins.

Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29F160TE/BE is erased when shipped from the factory.

The device features single 5.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

comleted, the device internally resets to the read mode.

The MBM29F160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any Embedded

Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the

read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during

the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read

mode and will have erroneous data stored in the address locations being programmed or erased. These locations

need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up

firmware from the Flash memory.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The MBM29F160TE/BE memory electrically erases all bits

within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word

at a time using the EPROM programming mechanism of hot electron injection.

* :

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

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