MBM29DL640E12TN datasheet, PDF

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MBM29DL640E12TN: Description64 M (8 M X 8/4 M X 16) BIT Dual Operation; Categorystorage storage; File Size337KB，71 Pages; ManufacturerFUJITSU; Websitehttp://edevice.fujitsu.com/fmd/en/index.html

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MBM29DL640E12TN Overview

64 M (8 M X 8/4 M X 16) BIT Dual Operation

MBM29DL640E12TN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	FUJITSU
Objectid	1912327746
Parts packaging code	TSOP1
package instruction	PLASTIC, TSOP1-48
Contacts	48
Reach Compliance Code	unknow
ECCN code	3A991.B.1.A
compound_id	9769869
Maximum access time	120 ns
Other features	CONFIGURABLE AS 8M X 8
Spare memory width	8
startup block	BOTTOM/TOP
command user interface	YES
Universal Flash Interface	YES
Data polling	YES
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	18.4 mm
memory density	67108864 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	16,126
Number of terminals	48
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	8K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.058 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
switch bit	YES
type	NOR TYPE
width	12 mm

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20887-1E

FLASH MEMORY

CMOS

64 M (8 M

8/4 M

16) BIT

Dual Operation

MBM29DL640E

80/90/12

DESCRIPTION

The MBM29DL640E is a 64 M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 Mwords

of 16 bits each. The device is offered in 48-pin TSOP (I) and 63-ball FBGA packages. This device is designed to

be programmed in system with 3.0 V V

supply. 12.0 V V

and 5.0 V V

are not required for write or erase

operations. The device can also be reprogrammed in standard EPROM programmers.

The device is organized into four physical banks: Bank A, Bank B, Bank C and Bank D, which can be considered

to be four separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu’s

standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access

from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simulta-

neously taking place on the other bank.

(Continued)

PRODUCT LINE UP

Part No.

Ordering Part No.

3.3 V

+0.3

−0.3

3.0 V

+0.6

−0.3



MBM29DL640E



120

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

PACKAGES

48-pin plastic TSOP (I)

Marking Side

48-pin plastic TSOP (I)

63-ball plastic FBGA

Marking Side

(FPT-48P-M19)

(FPT-48P-M20)

(BGA-63P-M02)

MBM29DL640E

80/90/12

(Continued)

In the device, a new design concept called FlexBank

Architecture is implemented. Using this concept the

device can execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and

Bank 2, a bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1.

(Refer to FUNCTIONAL DESCRIPTION for Simultaneous Operation.)

The standard device offers access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed

microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write

enable (WE) and output enable (OE) controls.

This device consists of pin and command set compatible with JEDEC standard E

PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the device is

similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded

Program Algorithm

which is an internal algorithm that automatically times the program pulse widths and verifies

proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is

accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm

which is an internal algorithm that automatically preprograms the array if it is not already programmed before

executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies

the proper cell margin.

A sector is typically erased and verified in 1.0 second (if already completely preprogrammed) .

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The device is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once a program or erase cycle has been completed,

the device internally resets to the read mode.

The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program

Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read

mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the

Embedded Program

Algorithm or Embedded Erase

Algorithm, the device is automatically reset to the

read mode and have erroneous data stored in the address locations being programmed or erased. These

locations need rewriting after the Reset. Resetting the device enables the system’s microprocessor to read the

boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of EPROM and E

PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits

within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word

at a time using the EPROM programming mechanism of hot electron injection.

*1: FlexBank

is a trademark of Fujitsu Limited.

*2: Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

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