ADVANCE INFORMATION
83C196LC, 83C196LD
CHMOS 16-BIT MICROCONTROLLER
Automotive
s
22 MHz operation
†
s
32 Kbytes of on-chip ROM (LC)
16 Kbytes of on-chip ROM (LD)
s
1 Kbyte of on-chip register RAM (LC)
384 bytes of on-chip register RAM (LD)
s
512 bytes of on-chip code RAM
(LC only)
s
Register-to-register architecture
s
Peripheral transaction server (PTS)
with high-speed, microcoded interrupt
service routines
s
Full-duplex serial I/O port with
dedicated baud-rate generator
s
Enhanced full-duplex, synchronous
serial I/O port (SSIO)
†
s
High-speed event processor array
— Six capture/compare channels
— Two compare-only channels
— Two 16-bit software timers
s
Programmable 8- or 16-bit external bus
s
Design enhancements for EMI
reduction
s
Oscillator failure detection circuitry
s
SFR register that indicates the source
of the last reset
s
Watchdog timer (WDT)
s
Cost reduced replacements for the
87C196JT and 87C196JR.
s
–40°
C to
+125°
C ambient temperature
s
52-pin PLCC package
12 MHz standard; 18 MHz and 22 MHz are speed
premium
NOTE
This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify
with your local Intel sales office that you have the latest datasheet before finalizing a
design.
The 83C196LC, 83C196LD are low-cost, pin-compatible replacements for the existing 87C196JT and
87C196JR, respectively. These products feature an enhanced synchronous serial I/O (SSIO) port for more
flexible communication to other devices. The enhanced SSIO is compatible with Motorola’s Serial Peripheral
Interface (SPI) protocol and National’s Microwire protocol. To optimize die size, the A/D converter was
removed for use in those applications that use an off-chip A/D converter.
The MCS
®
96 microcontroller family members are all high-performance microcontrollers with 16-bit CPUs.
The 83C196LC, 83C196LD are composed of a high-speed core with the following peripherals: an
asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an
additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter
structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O
for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs;
and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS).
The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes
of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration
of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming
language.
COPYRIGHT © INTEL CORPORATION, 1996
December 1996
Order Number: 272805-001
FPGA/CPLD
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