FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13602-4E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16L MB90670/675 Series
MB90671/672/673/T673/P673 (MB90670 Series)
MB90676/677/678/T678/P678 (MB90675 Series)
s
DESCRIPTION
The MB90670/675 series is a member of 16-bit proprietary single-chip microcontroller F
2
MC*
1
-16L family
designed to be combined with an ASIC (Application Specific IC) core. The MB90670/675 series is a high-
performance
general-purpose 16-bit microcontroller for high-speed real-time processing in various industrial equipment, OA
equipment, and process control.
The instruction set of F
2
MC-16L CPU core inherits AT architecture of F
2
MC-8 family with additional instruction
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and
enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word
data (32-bit).
The MB90670/675 series has peripheral resources of UART0, UART1(SCI), an 8/10-bit A/D converter, an
8/16-bit PPG timer, a 16-bit reload timer, a 24-bit free-run timer, an output compare (OCU), an input capture
(ICU), DTP/external interrupt circuit, an I
2
C*
2
interface (in MB90675 series only). Embedded peripheral
resources performs data transmission with an intelligent I/O service function without the intervention of the CPU,
enabling real-time control in various applications.
*1: F
2
MC stands for FUJITSU Flexible Microcontroller.
*2: Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these
components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as
defined by Philips.
s
PACKAGE
80-pin Plastic LQFP
80-pin Plastic QFP
100-pin Plastic LQFP
100-pin Plastic QFP
(FPT-80P-M05)
(FPT-80P-M06)
(FPT-100P-M05)
(FPT-100P-M06)
MB90670/675 Series
s
FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at
Vcc of 5.0 V)
• CPU addressing space of 16 Mbytes
Internal addressing of 24-bit
External accessing can be performed by selecting 8/16-bit bus width (external bus mode)
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
High code efficiency
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt function
8 levels, 32 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI
2
OS)
• Low-power consumption (standby) mode
Sleep mode (mode in which CPU operating clock is stopped)
Timebase timer mode (mode in which other than oscillation and timebase timer are stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware standby mode
• Process
CMOS technology
• I/O port
MB90670 series: Maximum of 65 ports
MB90675 series: Maximum of 84 ports
• Timer
Timebase timer/watchdog timer: 1 channel
8/16-bit PPG timer: 8-bit
×
2 channels or 16-bit
×
1 channel
16-bit reload timer: 2 channels
24-bit free-run timer: 1 channel
• Input capture (ICU)
Generates an interrupt request by latching a 24-bit free-run timer counter value upon detection of an edge
input to the pin.
• Output compare (OCU)
Generates an interrupt request and reverse the output level upon detection of a match between the 24-bit free-
run timer counter value and the compare setting value.
• I
2
C interface (in MB90675 series only)
Serial I/O port for supporting Inter IC BUS
(Continued)
2
MB90670/675 Series
(Continued)
• UART0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used.
• UART1 (SCI)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial transmission (I/O extended serial) can be selectively used.
• DTP/external interrupt circuit (4 channels)
A module for starting extended intelligent I/O service (EI
2
OS) and generating an external interrupt triggered
by an external input.
• Wake-up interrupt
Receives external interrupt requests and generates an interrupt request upon an “L” level input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8-bit or 10-bit resolution can be selectively used.
Starting by an external trigger input.
3
MB90670/675 Series
s
PRODUCT LINEUP
• MB90670 series
Part number
Item
MB90671
MB90672
Mask ROM products
MB90673
MB90T673
External ROM
product
MB90P673
One-time PROM
product
48 Kbytes
Classification
ROM size
RAM size
16 Kbytes
640 bytes
32 Kbytes
1.64 Kbytes
48 Kbytes
External ROM
2 Kbytes
CPU functions
Number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.5
µs
(at machine clock of 16 MHz, minimum value)
General-purpose I/O ports (CMOS output): 57
General-purpose I/O ports (N-ch open-drain output): 8
Total: 65
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (4800 Kbps to 500 kbps)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
Clock synchronized transmission (500 Kbps to 2 Mbps)
Clock asynchronized transmission (2400 Kbps to 62500 bps)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
Conversion precision: 10-bit or 8-bit selectable
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
Number of channels: 2
8-bit or 16-bit PPG operation
A pulse wave of given intervals and given duty ratios can be output.
Pulse cycle: 125 ns to 16.78 s (at oscillation of 4 MHz, machine clock of 16 MHz)
Number of channels: 2
16-bit reload timer operation
Interval: 125 ns to 131 ms (at machine clock of 16 MHz)
External event count can be performed.
Number of channel :1
Overflow interrupts or intermediate bit interrupts may be generated.
Number of channels: 8
Pin input factor: A match signal of compare register
Ports
UART0
UART1 (SCI)
8/10-bit A/D converter
8/16-bit PPG timer
16-bit reload timer
24-bit free-run timer
Output compare unit
(OCU)
(Continued)
4
MB90670/675 Series
(Continued)
Part number
Item
Input capture unit (ICU)
Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
Number of inputs: 4
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI
2
OS) can be used.
Number of inputs: 8
Started by an “L” level input.
An interrupt generation module for switching tasks used in real-time operating
systems.
None
18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Sleep/stop/CPU intermittent operation/timebase timer/hardware stand-by
CMOS
2.7 V to 5.5 V
MB90671
MB90672
MB90673
MB90T673
MB90P673
DTP/external interrupt circuit
Wake-up interrupt
Delayed interrupt generation
module
I
2
C interface
Timebase timer
Watchdog timer
Low-power consumption
(standby) mode
Process
Operating voltage*
* : Varies with conditions such as the operating frequency. (See section “s Electrical Characteristics.”)
5
京公网安备 11010802033920号
EEWORLD
