70V658S10BFG datasheet, PDF - EEWORLD Datasheet

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70V658S10BFG: DescriptionCABGA-208, Tray; Categorystorage storage; File Size407KB，25 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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70V658S10BFG Overview

CABGA-208, Tray

70V658S10BFG Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	CABGA
package instruction	TFBGA, BGA208,17X17,32
Contacts	208
Manufacturer packaging code	BFG208
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Samacsys Description	CHIP ARRAY BGA 15.0 X 15.0 MM X 0.8 MM P
Maximum access time	10 ns
I/O type	COMMON
JESD-30 code	S-PBGA-B208
JESD-609 code	e1
length	15 mm
memory density	2359296 bit
Memory IC Type	DUAL-PORT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	208
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA208,17X17,32
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.015 A
Minimum standby current	3.15 V
Maximum slew rate	0.5 mA
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm
Base Number Matches	1

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IDT70V659/58/57S

HIGH-SPEED 3.3V

128/64/32K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 10/12/15ns (max.)

– Industrial: 12/15ns (max.)

Dual chip enables allow for depth expansion without

external logic

IDT70V659/58/57 easily expands data bus width to 72 bits

or more using the Master/Slave select when cascading

more than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

◆

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

LVTTL-compatible, single 3.3V (±150mV) power supply for

core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 208-pin Plastic Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Functional Block Diagram

B BBB

E EEE

3 21 0

R RRR

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_L Dout18-26_R

Dout27-35_L Dout27-35_R

128/64/32K x 36

MEMORY

ARRAY

I/O

0L-

I/O

35L

Di n_L

Di n_R

I/O

0R -

I/O

35R

16 L(1)

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

16R(1)

R/W

BUSY

L(2,3)

SEM

INT

L(3)

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

M/S

BUSY

R(2,3)

SEM

INT

R(3)

TDI

TDO

JTAG

TMS

TCK

TRST

4869 drw 01

NOTES:

1. A

is a NC for IDT70V658. Also, Addresses A

and A

are NC's for IDT70V657.

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

JUNE 2018

DSC-4869/8

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