K7B203625B
K7B203225B
K7B201825B
64Kx36/x32 & 128Kx18 Synchronous SRAM
64Kx36/x32 & 128Kx18-Bit Synchronous Burst SRAM
FEATURES
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V+0.3V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7B203625B, K7B203225B and K7B201825B are
2,359,296 bits Synchronous Static Random Access Memory
designed to support zero wait state performance for advanced
Pentium/Power PC based system. And with CS
1
high, ADSP is
blocked to control signals.
It can be organized as 64K(128K) words of 36(32/18) bits. And
it integrates address and control registers, a 2-bit burst address
counter and high output drive circuitry onto a single integrated
circuit for reduced components counts implementation of high
performance cache RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B203625B, K7B203225B and K7B201825B are imple-
mented with SAMSUNG′s high performance CMOS technology
and is available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -65 -75 -80 Unit
t
CYC
t
CD
t
OE
7.5 8.5 10
6.5 7.5 8.0
3.5 3.5 4.0
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
A′0~A′1
COUNTER
A0~A1
64Kx36/32 , 128Kx18
MEMORY
ARRAY
ADSP
A0~A15
or A0~A16
ADDRESS
REGISTER
A2~A15
or A2~A16
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
DATA-IN
REGISTER
CONTROL
REGISTER
or DQa0 ~ DQb7
DQPa ~ DQPb
CONTROL
LOGIC
OUTPUT
BUFFER
36/32 or 18
-3-
Jan 2002
Rev 0.0
Recruitment
京公网安备 11010802033920号
EEWORLD
