IRHLNA797064 datasheet, PDF - EEWORLD Datasheet

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IRHLNA797064: DescriptionPower Field-Effect Transistor, 56A I(D), 60V, 0.015ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, HERMETIC SEALED, CERAMIC, SMD-2, 3 PIN; CategoryDiscrete semiconductor The transistor; File Size199KB，9 Pages; ManufacturerInfineon; Websitehttp://www.infineon.com/

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IRHLNA797064 Overview

Power Field-Effect Transistor, 56A I(D), 60V, 0.015ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, HERMETIC SEALED, CERAMIC, SMD-2, 3 PIN

IRHLNA797064 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	CHIP CARRIER, R-CBCC-N3
Reach Compliance Code	compliant
ECCN code	EAR99
Avalanche Energy Efficiency Rating (Eas)	1060 mJ
Shell connection	DRAIN
Configuration	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	60 V
Maximum drain current (Abs) (ID)	56 A
Maximum drain current (ID)	56 A
Maximum drain-source on-resistance	0.015 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	R-CBCC-N3
JESD-609 code	e0
Number of components	1
Number of terminals	3
Operating mode	ENHANCEMENT MODE
Maximum operating temperature	150 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Polarity/channel type	P-CHANNEL
Maximum power dissipation(Abs)	250 W
Maximum pulsed drain current (IDM)	224 A
Certification status	Not Qualified
surface mount	YES
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
transistor applications	SWITCHING
Transistor component materials	SILICON
Base Number Matches	1

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PRELIMINARY

PD-97174A

RADIATION HARDENED

LOGIC LEVEL POWER MOSFET

SURFACE MOUNT (SMD-2)

Product Summary

Part Number

Radiation Level

IRHLNA797064 100K Rads (Si)

IRHLNA793064

300K Rads (Si)

DS(on)

0.015Ω

-56A*

2N7622U2

IRHLNA797064

60V, P-CHANNEL

TECHNOLOGY

SMD-2

International Rectifier’s R7

Logic Level Power

MOSFETs provide simple solution to interfacing

CMOS and TTL control circuits to power devices in

space and other radiation environments. The

threshold voltage remains within acceptable

operating limits over the full operating temperature

and post radiation. This is achieved while maintaining

single event gate rupture and single event burnout

immunity.

These devices are used in applications such as

current boost low signal source in PWM, voltage

comparator and operational amplifiers.

Features:

5V CMOS and TTL Compatible

Fast Switching

Single Event Effect (SEE) Hardened

Low Total Gate Charge

Simple Drive Requirements

Ease of Paralleling

Hermetically Sealed

Ceramic Package

Surface Mount

Light Weight

Absolute Maximum Ratings

Parameter

ID @VGS = -4.5V,TC = 25°C Continuous Drain Current

ID @VGS = -4.5V,TC = 100°C Continuous Drain Current

IDM

Pulsed Drain Current

PD @ TC = 25°C

VGS

EAS

IAR

EAR

dv/dt

T STG

Max. Power Dissipation

Linear Derating Factor

Gate-to-Source Voltage

Single Pulse Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

Peak Diode Recovery dv/dt

Operating Junction

Storage Temperature Range

Pckg. Mounting Surface Temp.

Weight

* Current is limited by package

For footnotes refer to the last page

300 (for 5s)

3.3 (Typical)

-56*

-224

250

2.0

±10

1060

-56

-3.7

-55 to 150

Pre-Irradiation

Units

W/°C

V/ns

°C

www.irf.com

03/01/11

IRHLNA797064 Related Products

	IRHLNA797064	2N7622U2
Description	Power Field-Effect Transistor, 56A I(D), 60V, 0.015ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, HERMETIC SEALED, CERAMIC, SMD-2, 3 PIN	Power Field-Effect Transistor, 56A I(D), 60V, 0.015ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, HERMETIC SEALED, CERAMIC, SMD-2, 3 PIN
Is it Rohs certified?	incompatible	incompatible
package instruction	CHIP CARRIER, R-CBCC-N3	CHIP CARRIER, R-CBCC-N3
Reach Compliance Code	compliant	compli
ECCN code	EAR99	EAR99
Avalanche Energy Efficiency Rating (Eas)	1060 mJ	1060 mJ
Shell connection	DRAIN	DRAIN
Configuration	SINGLE WITH BUILT-IN DIODE	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	60 V	60 V
Maximum drain current (Abs) (ID)	56 A	56 A
Maximum drain current (ID)	56 A	56 A
Maximum drain-source on-resistance	0.015 Ω	0.015 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	R-CBCC-N3	R-CBCC-N3
JESD-609 code	e0	e0
Number of components	1	1
Number of terminals	3	3
Operating mode	ENHANCEMENT MODE	ENHANCEMENT MODE
Maximum operating temperature	150 °C	150 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
Package shape	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Polarity/channel type	P-CHANNEL	P-CHANNEL
Maximum power dissipation(Abs)	250 W	250 W
Maximum pulsed drain current (IDM)	224 A	224 A
Certification status	Not Qualified	Not Qualified
surface mount	YES	YES
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD	NO LEAD
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
transistor applications	SWITCHING	SWITCHING
Transistor component materials	SILICON	SILICON
Base Number Matches	1	1

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