notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
1
IS43LR16800D, IS43LR32400D
FUNCTIONAL BLOCK DIAGRAM (8Mx16)
CLK
CLK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE REGISTER
AND EXTENDED
MODE REGISTER
DATA IN
BUFFER
16
16
2
LDM, UDM
REFRESH
CONTROLLER
UDQS, LDQS
2
I/O 0-15
SELF
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
REFRESH
14
CONTROLLER
16
DATA OUT
BUFFER
V
DD
/V
DDQ
V
ss
/V
ss
Q
16
REFRESH
COUNTER
2
4096
4096
4096
4096
12
ROW DECODER
MULTIPLEXER
12
MEMORY CELL
ARRAY
14
ROW
ADDRESS
LATCH
12
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
512
(x16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
9
2
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
PIN CONFIGURATION:
Package Code B: 60-ball FBGA (top view)
(8mm x 9mm Body, 0.8mm Ball Pitch)
Top View
(Balls seen through the package)
1
2
3
4
5
6
7
8
9
60-Ball
A
B
C
D
E
F
G
H
J
K
1
A
B
C
D
E
F
G
H
J
K
VSS
2
3
7
DQ1
DQ3
DQ5
DQ7
NC
WE
CS
A10/AP
A2
8
DQ0
DQ2
DQ4
DQ6
LDM
CAS
BA0
A0
A3
9
VDD
VSSQ
VDDQ
VSSQ
VDD
RAS
BA1
A1
VDD
DQ15 VSSQ VDDQ
VDDQ DQ13 DQ14
VSSQ DQ11 DQ12
VDDQ
VSS
CKE
A9
A6
VSS
DQ9
UDM
CK
A11
A7
A4
DQ10
DQ8
NC
CK
NC
A8
A5
VSSQ UDQS
LDQS VDDQ
PIN DESCRIPTION: for x16
A0-A11
A0-A8
BA0, BA1
DQ0 – DQ15
CK, CK
CKE
CS
CAS
RAS
WE
LDM, UDM
LDQS, UDQS
VDD
VDDQ
VSS
VSSQ
NC
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Column Address Strobe Command
Row Address Strobe Command
Write Enable
Data Write Mask
Data Strobe
Power
Power Supply for I/O Pins
Ground
Ground for I/O Pins
No Connection
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
3
IS43LR16800D, IS43LR32400D
PIN CONFIGURATION:
Package Code B: 90-ball FBGA (top view)
(8mm x 13mm Body, 0.8mm Ball Pitch)
Top View
(Balls seen through the package)
90-Ball
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
2
3
DQ30
DQ28
DQ26
NC
CK
NC
A8
A5
DQ8
DQ10
DQ12
DQ14
7
DQ17
DQ19
DQ21
NC
WE
CS
A10/AP
A2
DQ7
DQ5
DQ3
DQ1
8
9
VDD
DQ31 VSSQ VDDQ DQ16
VDDQ DQ29
VSSQ DQ27
VDDQ DQ25
VDD
CKE
A9
A6
A4
VDDQ
DM3
CK
A11
A7
DM1
DQ9
DQ18 VSSQ
DQ20 VDDQ
DQ22 VSSQ
DM2
CAS
BA0
A0
DM0
DQ6
DQ4
DQ2
DQ0
VSS
RAS
BA1
A1
A3
VSSQ
VDDQ
VSSQ
VDD
VSSQ DQS3 DQ24
DQ23 DQS2 VDDQ
VSSQ DQS1
VSSQ DQ11
VDDQ DQ13
VSS
DQS0 VDDQ
DQ15 VSSQ VDDQ
PIN DESCRIPTION: for x32
A0-A11
A0-A7
BA0, BA1
DQ0 – DQ31
CK, CK
CKE
CS
CAS
RAS
WE
DM0 – DM3
DQS0 – DQS3
VDD
VDDQ
VSS
VSSQ
NC
4
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Column Address Strobe Command
Row Address Strobe Command
Write Enable
Data Write Mask
Data Strobe
Power
Power Supply for I/O Pins
Ground
Ground for I/O Pins
No Connection
Integrated Silicon Solution, Inc.
Rev. 00D
02/03/09
IS43LR16800D, IS43LR32400D
Symbol
CK, CK
Type
Input
Description
Clock: CK and CK are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Input and output data is referenced to the crossing of CK and CK (both directions of
crossing). Internal clock signals are derived from CK/ CK.
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
POWERDOWN (row ACTIVE in any bank). CKE is synchronous for all functions except
for SELF REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding
CK, CK and CKE, are disabled during power-down and self refresh mode which are
contrived for low standby power consumption.
Chip Select: CS enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when
CS is registered HIGH. CS
provides for external bank selection on systems with multiple banks. CS is considered
part of the command code.
WE Input Command Inputs: RAS, CAS
and
WE (along with CS) define the command
being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM
is sampled on both edges of DQS. Although DM pins are input-only, the DM loading
matches the DQ and DQS loading.
For x16 devices, LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the
data on DQ8-DQ15.
For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to
the data on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, and DM3
corresponds to the data on DQ24-DQ31.
BA0, BA1
A [n:0]
Input
Input
Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
Address Inputs: provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ / WRITE commands, to select one
location out of the memory array in the respective bank. The address inputs also
provide the opcode during a MODE REGISTER SET command.
Data Bus: Input / Output
CKE
Input
CS
Input
RAS, CAS,
WE
DM for x16;
LDM, UDM for
x32; DM0-DM3
Input
Input
DQ for x16;
DQ0-DQ15 for
x32;
DQ0-DQ31
DQS for x16:
LDQS,UDDS
for x32:
DQS0-DQS3
I/O
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data,
centered with write data. Used to capture write data.
For x16 device, LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to
the data on DQ8-DQ15.
For x32 device, DQS0 corresponds to the data on DQ0-DQ7, DQS1 corresponds to
the data on DQ8-DQ15, DQS2 corresponds to the data on DQ16-DQ23, and DQS3
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